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8K STORAGE OPERATION
•
A complete storage cycle consists of a read cycle and
a write cycle.
•
In a given storage cycle, drive current flows through
the selected drive lines in one direction for read, and
in the opposite direction for write.
•
At the end of the read cycle, all cores at the addressed
position are logical O.
•
An interlock in the 2030 ensures that a write cycle
occurs between read cycles so a storage position is not
left blank.
•
The inhibit drivers turn on for those planes where the
core
is
to be left at logical O.
Description (Figure 2-79)
When the 2030 places an address into the M-
and N-registers and requests a read cycle,
the storage clock is started.
The address
lines from the M- and N-registers combine
with clock timing to turn on
x-
and Y-read
current sources
x-
and Y-read gates, and X-
and Y-read control drivers.
This causes
read current to flow through one X-winding
and one Y-winding.
The coincident read
drive currents cause all the cores at the
addressed position to experience a magnetic
effect great enough to flip all cores to
the logical 0 magnetic state.
Any cores
that change magnetic state from logi,cal 1
to logical 0 cause a current pulse to be
induced onto the sense winding.
The clock
signals combine with the M- and N-register
bits to gate the appropriate sense ampli-
fiers.
The amplified sense bits cause data
latches to set on.
Toward the end of the
read cycle, the 2030 is signalled that the
data is ready.
At this time, all cores in
the addressed position are set to logical
O.
This means the addressed position con-
tains an even parity byte (000000000).
The write call signal from the 2030
starts the storage clock and conditions a
write cycle.
The M- and N-register contain
the same address as during the preceding
read cycle.
However, the address bits now
combine with write timings to turn on X-
and Y-write current sources, X- and Y-write
gates, and X- and Y-write control drivers.
The result is that current flows in the op-
posite direction through the same two drive
.lines as during the preceding read cycle.
With no further control, this would result
in all cores in the addressed position
being set to logical 1.
However, during a
write cycle, it is necessary to set some
cores to logical 1 while le'aving the other
cores at logical
o.
The byte of informa-
tion to be stored in core storage was
placed in the R-register by the 2030 before
the storage write cycle was initiated.
To
store the correct byte, the byte in the R-
register controls the appropriate set of
inhibit drivers so inhibit current will
flow in the bit planes where the core is to
remain logical 0, and inhibit current is
blocked in the bit-planes where the core is
to be flipped to logical 1.
Thus, if the
R-register contains the byte POOIOII01, the
0-, 1-, 3-, and 6-bit inhibit drivers are
turned on while the P-, 2-, 4-, 5-, and 7-
bit inhibit drivers are blocked from turn
ing on.
The result is that although co-
incident write current flows through all
cores in the addressed position, only those
cores that experience no inhibit current
are set to logical 1.
This causes the byte
.that was in the R-register to be stored in
the addressed storage location.
2-81
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