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Del
T
0
ay
ap
ns
Delay Tap 1100 ns
Delay Tap 75 ns
Delay Tap 775 ns
Delay Tap 525 ns
Delay Tap 775 ns
Delay Tap 525 ns
Delay Tap 800 ns
Delay Tap 750 ns
Delay Tap 925 ns
1
Set Rd
Delay Tap 300 ns
Read Call
Latches
--FL-~-
Set Wr
Delay Tap 1200 ns
Write Call
Latches
Delay Tap 200 ns
Delay Tap 950 ns
Delay Tap 150 ns
Delay Tap 775 ns
Delay Tap 300 ns
Delay Tap 750 ns
Delay Tap 300 ns
Delay Tap 750 ns
1
Delay Tap 500 ns
Delay Tap 150 ns
Figure 2-55.
Memory Clock
2-46
A
r -
--FL---
A
A
r -
f - -
FL-'--
A
A
f---
r--FL---
A
A
r -
- - FL---
A
A
r -
--FL---
A
IA
L -
--FL--
A
r -
f---FL---
A
A
r -
,..---FL---
A
A
f---
- - FL---
A
A
r -
f---
FL---
A
A
L -
--FL---
I - -
Phase
Read
I - -
Read I
Read 2
1--1
Strobe
1---:
I----
~
I - -
- I
Data
Ready
Phase
Write
nhibit
- '
Write I
-
Write 2
--.J
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