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Address Decode
and Drive
Not M-reg
O-bit
p
p
1st 32K
Core Storage
7
7
2nd 32K
Core Storage
Address Decode
and Drive
M-reg
O-bit
P
7
P
7
':""'--"--f -=- ':"""-f"---:'"
s
MN Bus
Figure 2-83.
65K Addressing
Circuit Objectives
Circuit control for the 65K storage unit is
dependent on the Go signal, developed from
theM-register O-bit on logic page MM142.
This same page applies to both the first
32K and the second 32K.
For the first 32K,
the M-register O-bit is inverted to
p~oduce
the Go signal.
The M-register O-bit is re-
quired to produce Go for the second 32K.
Thus, Go will be active. for either one unit
5
or the other, but never both.
In the unit
where the Go signal is down, the following
functions are blocked:
Data Ready on Read Cycle (MMI13)
x-
and Y-Source Drivers on Read Cycle
(MM252)
Strobe on Read Cycle (MM692)
Clock Start on Write Cycle (MMI13)
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