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storage consists of selecting the
and
lines from the
address in ____ _
3.
An X-line is conditioned by what
bits in the address?
4.
A Y-line is conditioned by what
bits in the address?
5.
What must be accomplished to read
out a core location?
6.
A 32K storage array has
set
(S)
of X
lines and
set
(S)
of Y lines, and
phase reversal
planes.
1.
Data coming from storage is read
into the
register.
8.
When is current induced in the
inhibit-sense line during read
time?
9.
Noise is eliminated from the data
pulse during reading through use of
a
pulse.
10.
To write a bit in core, inhibit
current must_(flow, not flow).
11.
What is the function of the dummy
planes placed between each 8K of
the 32K storage array?
12.
The purpose of the early-MO pulse
is to allow correct
selection
before the storage cycle starts.
13 •. To select the upper 32K of a 64K
storage array, the
bit of the
address must be ____ _
14.
How many gate decode switches are
needed to control X-Line selection
in a 16K array?
.
15.
How many gate decode switches are
needed to control Y-Line selection
in a 16K array?
16.
A read gate transistor must have
both the
and
conditioned to
cond~
11.
What is the purpose of an inhibit
driver?
18.
Where can a CEfind troubleshooting
aids for fixiD9 core-storage
troubles?
2-62
19.
Read 1 conditions the
Read 2 conditions the -----
MEMORY CONTROL
MN-REGISTER
lines.
lines.
The main MN-register function is to
supply a two-byte address to the core
storage unit.
The MN-register consists
of two separate 9-bit registers (8 bits
plus parity bit).
The parallel output
of these registers is fed to the core
storage addressing circuitry over the
CPU to memory interface.
There is no
gate at the output of the MN-register.
Whatever is stored in the MN-register is
present at the input of the memory
addressing circuitry.
Therefore, to
control the address presented to the
core storage unit, the CPU controls the
address in MN by controlling the data at
the
~nput
of MN, and by controlling the
time when MN-data can be changed.
The input to the MN-register is the
l8-bit wide MN-register assembler bus.
Feeding this bus are seven possible
sources for MN data.
These are:
I.J-registers
UV-registers
LT-registers
GUV-registers
HUV-registers
Console SWitches A, B, C, and 0
Next-address information from
the read-only storage unit.
When the CPU wishes to change an
address in MN, one of the previously
mentioned sources is gated onto theMN
assembler bus.
The MN-registers are
polarity hold latches.
To change the
information in these latches, the CPU
must activate the control line during
the time when the MN assembler bus is
active.
If the CPU clock is running,
the control line is activated at T1-time
of a read cycle.
The control line is
not activated during a write or store
cycle.
This is because core storage
read-out is destructive:
all cores must
be set to logical zero to read out
information.
Thus, if we were to read
out a position and change the MN address
before writing something back, the posi-
tion read out would have all cores set
to zero, and an R-register parity error
would occur the next time that position
is read out.
If the CPU clock is not
running, the MN-register can be set from
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