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1.
An 8 bit Op Code.
2.
A 4 bit register address for 1st
operand.
(Destination)
3.
A 4 bit register address for 2nd
operand.
(Source)
Instructions that involve register to
register operations are considered to be
of the RR format.
RR Format
r---------T----T----1
I
Op Code
I
Rl
I
R2
I
L-_______ -L-___
~
____
J
Bits 0 and 1 of the Op Code indicate
the length of the instruction and the
location of the operands.
For the RR
format, bits
0
and
1
are
00.
The 2nd byte of the RR format is
divided into two fields:
Rl and R2.
The Rl field gives the register address
of the first operand while the R2 field
is the address of the 2nd operand.
The
numbers in the address fields of the RR
formats (and all other formats) indicate
whether the operand is the 1st or 2nd
(and is in some cases, the 3rd) operand.
For most operations, the results replace
the 1st operand.
RX FORMAT:
Instructions which are two
halfwords in length may have
3
different
formats.
As you recall, if bits
0
and
1
of the Op Code are either
01
or
10,
the
instruction is two halfwords in length.
Furthermore if bits
0, 1
of the Cp Code
is 01, it indicates a specific format
known as the RX format.
RX Format
r--------~-----~---~-~------T------l
I
Op Code
I
Rl
I
X2
I
B2
I
D2
I
l ________
~
_____
~
______
~
___
--~------J
Gen.
Reg.
Index
Reg.
Base
Reg.
Displace-
ment
In the RX format, the effective
address is generated by adding the con-
tents of the base register and the index
register to the displacement.
The RX
format is used for storage to register
operations.
The destination register
address is specified by the R1 field.
r---------T------T------T------T------,
I
ADD
I
3
I
7
I
4
I
1024
I
________
~
______
~
______
~
______
~
______ J
For the above RX-type instruction,
the storage address is generated by
adding the low order 24 bits of the
contents of registers 7 and
4
and the
displacement value of 1024.
The storage
(source) operand is added to the con-
tents of register
3
and the sum is
placed in register 3.
RS FORMAT:
Storage to Register instruc-
tions in which the storage address does
not include an indexing factor are
called the RS format.
The
4
bits nor-
mally used for the X2 field are used for
a 3rd Operand.
r---------T-----~------T------T------l
I
Op Code
I
Rl
I
R3
I
B2
J
D2
I
l _________
~
_____
~
____
~
______
~
______
J
RS Format
The RS Format is identified by a 10
in bits 0 and
1
of the Op Code.
The R3
field in the RS Format specifies the
general register used for the 3rd oper-
and.
In some RS instructions, the R3
field is ignored.
An example of an
instruction which uses the R3 field is
an instruction called Load Multiple.
In
the Load Multiple instruction, the data
in main storage is loaded (or placed)
into the general registers.
Loading
begins with the register specified by
the R1 field and continues consecutively
until the register specified by the R3
field has been loaded.
For Example:
r---------T------T------T------~----l
I
Op Code
I
4
I
7
I
0
0100
I
l _________
~
_____
~
______
i _ _ _ _ _ _ _ _ _ _ _
J
Load Multiple
In the above example the effective
storage address is
0100.
This is
because register 0 is specified as the
base register and its contents are
ignored.
In the above example, registers
4
through 7 will be loaded with the. data
in main storage.
As each register can
hold one full word, registers 4-7 will
be loaded with the data in storage loca-
tion
0100
through 0115.
(Each storage
address represents a byte of data.)
1-41
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