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STOP :KEY
•
Stops the CPU clock. at the end o.f
the instruction in process.
•
All pending interrupts are taken
before CPU clock is stopped.
•
Machine status is not effected.
•
Stop key is located on logic page PA
101.
Description
The CPU proceeds to the end of the
instruction in process at the time the
stop key is pressed.
All pending inter-
rupts are taken before the CPU clock is
stopped.
Once the clock is stopped, no
traps are allowed.
Any I/O operation in
process at the time the stop key is
pressed is allowed to finish before the
CPU clock is stopped.
If an I/O device
is involved in command or data chaining,
these chains are completed before the
clock is stopped.
When the CPU has stopped, the storage
address of the next instruction is dis-
played in the B and A registers.
DISPLAY :KEY
•
Allows a selected byte to be gated
to a display register.
•
Selected byte may be from any reg-
ister or from any core storage area.
•
CPU clock must be stopped, and allow
write latch must be off.
•
Display :Key located on logic page PA
Description
Because certain registers in the 2030 do
not have their own console indicators,
provision has been made to display these
registers in another way.
With the CPU
clock off, pressing the display key
caUses the contents of the register or
storage location specified by console
switch E to be displayed in a display
register.
An
~dditional
display feature occurs
when the
1-,
J-, U-, or V-registers are
selected.
If either the I- or J- reg-
ister is selected, both I and.J are
transferred to the M- and N-registers so
6-14
the entire address is displayed by the
M- and N-register indicators.
Similar-
if either the U- or V-registers is dis-
played via the A-register, then both U
and V are transferred to and displayed
by the M- and N-registers.
Note:
this
transfer of IJ or UV to MN during dis-
play takes place only if the allow write
latch is off and the CPU clock is
stopped.
Allow write must be off to
permit changing the address in MN.
To use the display feature, first
make sure that the CPU clock is stopped.
In addition, if a storage position or
the I-, J-, U- or. V-registers are to be
displayed, the allow write latch must be
off.
(The allow write latch lights the
Allow Write CPU status indicator on the
lower console indicator panel.)
Next,
set the display-store select switch,
switch E, to define the register or
storage area to be displayed.
If a
storage area is selected (main storage,
or auxiliary storage), or the storage
address must be set up in the main stor-
age address switches, switches A, B, C,
and D.
If a register is being
displayed, pressing the display key
gates the selected register into the
A-register for display.
No storage
cycle is taken.
If the I-, J-, U-, or
V-register is being displayed, pressing
the display key gates the selected reg-
ister to the A-register, and gates the
selected register and its complementing
register to the MN-registers for
display.
No storage cycle is taken.
If a storage location is being dis-
played, a storage read cycle is taken
followed by a storage write cycle.
This
retrieves the desired byte from storage
and places it into the R-register for
display.
When a storage location is
being displayed, where a program has
been halted, it is a good idea to note
the contents of the R-register prior to
the display operation.
Then, the R-
register can be restored prior to
reentering the program and starting the
CPU clock.
INTERVAL TIMER SWITCH
•
•
When on, the interval timer switch
allows the interval timer to
advance.
When off, the interval timer switch
prevents interval timer advance.
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