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Name
M-Register
Position
0
I
2
3
4
5
6
7
0
I
3
I
2
6
8
4
2
I
Binary
7
3
I
0
0
0
5
2
I
Value
6
8
9
9
4
2
I
5
2
6
8
4
2
6
8
4
2
6
8
4
Figure 2-47.
Storage Address Register
Thus far, we have discussed only the
basic or 8, 192-position block of core
storage.
To address this block requires
only the low-order 13 bits of the M- and
N-registers.
The remaining 3 high-order
bits are used to complete the addressing
scheme up to the maximum core storage
size available (65,536 bytes).
Address Decode
•
Address decode takes place for each
end of the drive lines.
•
Four drivers, 16 gate decodes, and
64 gate transistors for each end of
the X-drive lines.
•
Eight drivers, 16 gate decodes, and
128 gate transistors for each end of
the Y-drive lines.
•
The gate transistor, with both base
and emitter conditioned, is turned
on to supply drive current.
2-36
2
3
2
N-Register
3
4
5
6
7
I
6
8
4
2
I
The examples of Figures 2-45 and 2-46
assume certain address values to be
present at the input of the transistor
circuits.
Developing these address
values
fr~
the binary address presented
to the core storage unit is known as
address decoding.
There is address
decoding circuitry for the 64-line X-
dimension, and similar address decoding
circuitry for the 128-line Y-dimension.
min addition, further address decoding
takes place at each end of the lines.
One end is address decode for read, and
one end is address decode for write.
Read and write address decoding for the
X-dimension is shown in Figure 2-48.
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