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The location of the next instruction
to be fetched from main storage is indi-
cated by bits
40-63
of the PSw.
As you
learned earlier, main storage requires
binary addresses.
Bits 40-63 of the PSW
contain the 24 bit binary main storage
address of the next sequential instruc-
tion.
o
39 40
63
r---------T----------------------------,
I
I
l _________
~
____________________________ J
24-Bit Instruction Address
The PSW is a doubleword which
reflects the status and controls the
program currently being executed.
For
this reason, it is often referred to as
the current PSW.
Before examining more of the current
PSW, you may be wondering where this
doubleword is kept.
For one thing, the
current PSW does not use any of the 16
general registers or addressable loca-
tions in main storage.
It is kept in
some internal area or areas of the
System/360 that are not addressable by
the program.
Although the current PSW
may be scattered throughout the CPU, it
is considered as one doubleword of
information.
The instruction address portion of
the current PSW must be updated for each
instruction that is fetched and
executed.
That is,
i f
an RR type
instruction is fetched from location
1000, the instruction address portion of
the current PSW must be updated.
Since
an RR type instruction is one halfword
in length, the location of the next
sequential instruction would be 1002.
Thus the instruction address portion of
the PSW must be updated to contain 1002.
After the RR type instruction at
location 1000 has been executed, the
instruction address portion of the PSW
which contains 1002, will be used to
fetch the next instruction.
If the
instruction at location 1002 is the
RX
type, the instruction address portion of
the current PSW will then be changed to
1006.
Since instruction length is always a
multiple of halfwords, the instruction
address portion of the current PSW is
always updated by some multiple of 2.
The instruction address in the current
PSW is increased by 2, 4, or 6 depending
on bits 0 and 1 of the current
instruction's Op Code.
For example, if
bits
0
and 1 of the current
instruction's Op Code contain 11, the
instruction address in the current PSW
will be increased by 6.
1-45
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