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2
3
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8
9
10
11
12
13
First Two Micro-
Words of I-Phase
CPU Clock
Set ROAR
ROAR Go
SAL's Good
Orl
Reg Good
Read De lay li ne
Write De lay line
Read Call
Strobe
Data Ready
R Reg
Update J Reg
Write Call
Inhibit
Gate R-G
Set Destination
Cycle
Function
I
I
I
I
I
I
I
:
T2
:
T3
:
T 4
:
T 1
:
T2
:
T3
I
I
I
T1
T4
T 1
I
I
.lA
R1 R2
Op Code
:
T2
I
T3
T4
0100
I
I
0109
I
I
I
I
I
:
I
I
I
I
I
I
I
I
I
Read Word 1
I
I
I
I
I
IJ_MN
I
I
J + 0 + l_J
I
I
I
I
I
Write
I
o
.2
I
.4
I
.6
1.8
1.0
I
P
I
.4
I
.6
.2
'.8
I
1.0
,
I
i
I
I
I
I
I
I " "' ..
I-----Memory Read Cycle
- - - - - 1 ..
-i I ,
I
I
I
I
I
I
I
:
I
I
I
:
I
I
I
I
Execute Word 1
Read Word 2
I
I
I
I
" " ' 1
. .
> - - - -
Memory Write Cycle
.-j
I
I
I
I
n:
I
I
I
Op Code -lA
I
,
I
i
I
I
I
J
I
I
I
I
Execute Word 2
I
I
I
I
I
I
I
I
I
rGl
Pigure 3-58.
ROS to Memory Timings
T1
I
I
r
t:
3-81
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