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Interruption Source
Interruption Code
Mask
ILC
Instruct i on
Identification
PSW Bits 16-31
Bits
Set
Execution
Input/Output (Old PSW 56, New PSW 120)
Multiplex Channel
00000000
aaaaaaaa
0
x
Complete
Se lector Channe I 1
00000001
aaaaaaaa
1
x
Complete
Se lector Channe I 2
00000010
aaaaaaaa
2
x
Complete
Selector Channel 3
00000011
aaaaaaaa
3
x
Complete
Selector Channel 4
00000100
aaaaaaaa
4
x
Complete
Se lector Channe I 5
00000101
aaaaaaaa
5
x
Complete
Se lector Channe I 6
00000110
aaaaaaaa
6
x
Complete
-
-
' - - - -
- - , - -
Program (Old PSW 40, New PSW 104)
a
= VO
Device Address
Operation
00000000
00000001
1,2,3
Suppress
Privi leged Operation
00000000
00000010
1,2
Suppress
Execute
00000000
00000011
2
Suppress
Protection
00000000
00000100
0,2,3
Suppress/Terminate
Addressing
00000000
00000101
0,2,3
Suppress/Terminate
Speci fi cation
00000000
00000110
1,2,3
Suppress
Data
00000000
00000111
2,3
Terminate
Fixed-Point Overflow
00000000
00001000
36
1,2
Complete
Fixed-Point Divide
00000000
00001001
1,2
Suppres!V'Comp lete
Decimal Overflow
00000000
00001010
37
3
Complete
Decimal Divide
00000000
00001011
3
Suppress
Exponent Overflow
00000000
00001100
1,2
Terminate
Exponent Underflow
00000000
00001101
38
1,2
Complete
Signifi cance
60000000
00001110
39
1,2
Complete
Floating-Point Divide
00000000
00001111
1,2
Complete
Supervisor Call (Old PSW 32, New PSW 96)
Instruction Bits
00000000
rrrrrrrr
1
Complete
1 - - - - - - - - -
r
=
Bits 8-15 of Supervisor
Call Instruction
External (Old PSW 24, New PSW 88)
External Signal 1
00000000
xxxxxxxl
7
x
Complete
External Signal 2
00000000
xxxxxxlx
7
x
Complete
External Signal 3
00000000
xxxxxlxx
7
x
Complete
External Signal 4
00000000
xxxxlxxx
7
x
Complete
External Signal 5
00000000
xxx 1 xxxx
7
x
Complete
External Signal 6
00000000
xxlxxxxx
7
x
Complete
Interrupt Key
00000000
xlxxxxxx
7
x
Comp'lete
Timer
00000000
lxxxxxxx
7
x
_ _ Complete _ _ _
x
=
Unpredictable
Machine Check (Old PSW 48, New PSW 112)
Machine Malfunction
00000000
00000000
13
x
Terminate
Figure 1-30.
Interruption Code and Action Chart
PSW is located 64 higher than the cor-
responding old PSW.
Although an interrupt may be initiat-
ed by an instruction (such as when the
instruction supervisor call initiates a
supervisor interrupt), the actual stor-
ing and loading of the PSW is done auto-
matically by the internal
ci~cuitry
of
the System/360.
Although we state that interrupts
occur only at the end of an instruction
and never in the middle of one, this
might be a little misleading_
It is
definitely and absolutely true that the
current instruction will be completed
before an I/O, external, or supervisor
call interrupt is taken_
In the case of
program and machine interrupts (which
indicate programming and hardware
errors, respectively), the interrupt
1-55
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