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8 LOCAL STORAGE GATE TRANSISTORS
(4 CPU LOCAL, 4 MPX)
128 Y GATE TRANSISTORS
r-----------~A~----------~
, -_ _ _ _ _ _ _ _ _ _ _ _
~A~
_ _ _ _ _ _ _ _ _ _ _ _ _ _
~
16
Y
GATE
~~~ ~~
DECODE
SWITCHES
I
NOT NREG 181T
NOT NREG 081T
A
0-63
NOT M REG 7 81T
NOT M REG
6
BIT
NREG I BIT
NOT N REG 0 BIT
A
NOT M REG 7 BIT
64-127
NOT M REG 6 BIT
I
NOT NREG 1 BIT
N
REG 0 BIT
A
128-191
NOT
M
REG
7
BIT
NOT MREG6BIT
NREG I BIT
N REG 0 BIT
A
I
192-285
NOT
M
REG 7 BIT
NOT M REG 6 BIT
I
I
I
NREG I BIT
,
N REGO BIT
MREG7BIT
A
960-1023
M REG 6 BIT
READ
READ
A
A
f---
LOCAL STORAGE
MPX 1
2 LOCAL READ DRIVERS
Figure 2-53.
Local Storage Gate Decode
Figure 2-53 shows auxiliary Y read-
gate selection when the address 174 is
placed in the MN-register.
The Y gate-
decode switch that is turned on by the
MN-register contents conditions the
bases of 18 Y gate-transistors (16 main
Y gate-transistors and two auxiliary Y
gate- transistors).
However, only one Y
gate-transistor is further conditioned
by a Y-driver.
In this case, the
multiplexor read driver is turned on
because the M-register 3 bit is zero and
because the CPU Main-Auxiliary latch is
set to Auxiliary.
STORAGE CLOCR
•
There is a separate clock for the
core storage unit.
•
Delay lines produce timing pulses.
•
Control latches develop delay line
drive pulses.
~~ ~ ~~~~.
MAIN READ
MAIN READ
~
NOT MREG 5 BIT
A
M
REG 5
SIT
J
A
I -
NOT M REG 4 BIT
t--
MREG4BIT
NOT MREG 3 BIT
MREG3BIT
I
a
MAIN
Y
READ DRIVERS
•
Read and write clocking pulse latch-
es form storage drive pulses.
•
Clock started by signal from CPU.
•
Once started, clock operates for
complete cycle.
The core-storage unit is operated on a
cycle-by-cycle basis.
If a byte of
information is to be retrieved from the
core-storage unit, a read cycle is ini-
tiated.
During the subsequent read
cycle, a storage pOSition is addressed
and the byte of information stored in
that position is read out to the data
register.
If a byte of information is
to be placed into core storage, a.write
cycle is initiated.
During the subse-
quent write cycle, a storage position is
addressed and the desired information is
placed into the addressed byte location.
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