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To
T3
~
A
Micro Program
AND
I - - -
First Mach Chk Req
Entries
Mach Rst ' - - -
0
Priority
R
Latch
(Figure 3-56)
To Priority
roo-
PH
L - -
Pulse
0
Circuits
i---Fl--
. -
0
Load Req
R
.----
~
r-
PH
' - - -
1
Force IJ
~
PH
2
Any
Priority
Memory Wrap
Any Priority Pulse
latch
T1
-
~
OR
f - -
I -
-PH--
PH
Mach Rst
3
' - -
Memory Protect Req
~
T1
r - -
r -
A
PH
Proc Stop loop
Mach Rst
OR
r-
4
Active
Gt Sw to Wx
L - -
' - - -
Stop Req
WX SABC
~r--;;:--
~
r - -
PH
Tl
OR
f--
5
Mach Rst
--PH--
' - - -
' - -
~
Sel Ros Req
r-
(Not) H-Reg. 5
I---
~
PH
Priority
' - -
6
Reset
E--~
CD - 0101 (H)
Control
L..-ry
T4
r - - -
(Not) H-Reg 6
r-
t-
OR I--
MPX Share Req
~
Mach Rst
I---
-PH--
' - - -
' - - -
PH
7
L - -
Gate Switches to WX
Gt Switches to WX
~
Main
First Trap
PH
Micro
ROS Cyc:fe
8
Program
(Dead Cycle)
T1 T2 T3 T4 Tl T2 T3 T4 T1 T2
Mach Rst
' O RJ
Priority Stack
I
1
I
I
I
I
I
I
I
I
Latch
I
I
I
I
I
,
I I
I
r;;:-
I
I
I
Gt
Sw,to WX
I
I
Any Priority
I
I
I I
I
I
I
P4
latch
I
I
I
,
I I I
j
I
-
I
I
I
I
I
I
I
' - - -
Priority
I
I
I I I
I
I
I
I
I
I
r - -
Latch
I I I I T I
Not Allow Write
A
I
I
I
T3
f - -
Priority Reset
I I
I
I I
!
I
I
I
!
I I I
I
' - - -
Control
I
I
i
I
I
I
I
I
Figure 3-57.
Priority Stack Registers and Controls
3-79
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