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+:
A'
1+
.>
,
<,
l,
---D02
-I<]-~
~>
I
I
1
I
---B03
-1<]-1
i
H:~----,
}-I:>--B05-
---D04
-1<]--1
I
r
l
.
I
11_'
1
t----I P
1
_ _ _ D05
-1<]--'
j
,_',
'>
I
<
L_J
I'
-'-
1
=
1- 3V
Figure 2-12.
+AI
- - J 0 2
A
--B08
- - B I 2
A
- - J 0 2
- - B I 2
- - B I 3
Figure 2-13.
-AOI
OR
D I I - - -
REVIEW QUESTIONS - BASIC COMPONENTS
1.
A wedge on an output line desig-
nates the active output as
2.
A plus OR is the same as a
AND.
3.
Exclusive OR circuits have
input lines.
4.
The Exclusive OR is active when the
input levels are ______ __
5.
The time designated on an 55 block
is the
that the
~
____ __
is at its designated level.
6.
The time on a TD block is the
difference between the
level.
of the input pulse and the
of the designated output
7.
Three types of reRembering devices
are the
latch,
the
latch and the
8.
The Control line of a Polarity Hold
latch does not need to be active to
deactivate the output.
(True/False)
9.
The output of a Polarity Hold latch
will always follow the Data line.
(True/False) •
10.
The
requires a
latch back line.
CENTRAL PROCESSING UNIT (CPU) CLOCK
•
•
A 2-megacycle clock circuit produces
clock pulses P1, P2, P3, and P4.
The overlapping of 500 nanosecond P
pulses switch to form 250 nanosecond
1
timing pulses of Tl, T2, T3, and
T4.
•
E
pulses are distributed to all
large-boards, where the switching is
done near the boards that use the
particular
1
pulse.
The timing pulses for the IBM. 2030 Proc-
essing Unit, are derived from a 4-stage
overlapped latch-ring that uses five
nanosecond SLT circuitry_
(All other
portions of the machine use medium speed
30 nanosecond circuits.)
A 2-megacycle
crystal oscillator provides the basic
pulses for the latch ring.
Looking at
Figure 2-14, these oscillator pulses are
fed to the clock ring by two line names:
oscillator (Osc) and delayed-oscillator
(DIy OSC) _
Each of these lines have two
levels, plus and minus, which means that
there are a total of four lines from the
basic oscillator driving the clock.
2-5
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