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ROS is a capacitor storage device
which contains capacitors printed on a
card.
The output of ROS, as determined
by the capacitor cards, is latched in
sense amplifier latches (SAL'S). Defin-
ite fields in the cards are used to
control entry and exit of data to the
various registers and buses, Figure
1-25.
CORE STORAGE
•
Core storage is made of small
doughnut-shaped rings (magnetic
cores).
•
Capacities vary from
8,192
bytes to
65,536
bytes.
The basic storage unit of the Model
30
is made of small doughnut-shaped rings
which are used to store information.
This read-write storage is an eight bit
(plus parity) wide binary addressed
storage unit.
The size of the core
array can be expanded from the basic
8,192
bytes to a total of
65,536
bytes.
In addition to main storage, there
are
512
positions of storage in the
basic machine which are unaddressable as
far as the programmer is concerned.
These positions can only be used by
internal machine micro-programming.
These added positions give
256
positions
for CPU use and
256
positions for I/O
use.
The data flow ohart (Figure
1-25)
shows that there are two input lines to
storage and one output.
To locate data
in storage the address of the data must
be placed in the MN-register and decoded
by circuits which actually address the
proper byte in the core planes.
The
data -reads out- to the R-register which
is the storage data register.
Notice
also that in order to write into core
the data will come from the R-register
and enter the location in core addressed
by the MN register.
These three opera-
tions are instructed by micro-
programming through the use of ROS
control fields.
DATA BUSES
•
There are 7 general data buses which
move information throughout the
Control Processing Unit.
•
All buses are 9 bits wide except the
W-bus, which is 6 bits wide, includ-
ing the parity bit.
In Figure
1-25
the general data buses
are shown as wide data paths, only to
indicate that they receive or send data
to more than one register.
The actual
bit width of all buses is
8
(plus
parity) with the exception of the W bus
which is
5
bits, plus parity (bits
3
through 7 plus P) •
The MN and WX buses are 4 physical
buses feeding individual registers.
As
indicated in Figure
1-25,
the UV and IJ
registers are larger than the T-register
and yet they feed the same buses.
The
'I-register is programmed by ROS to
transfer data to the N-register while at
the same time the high order
8
bits of
the MN register are set to zero.
The
A-bus supplies data from all registers
to the A-register, while the B-bus
accepts data from only
3
registers and
then transfers it to the B-register.
The Z-bus is used to transfer data
back to various registers from ALU.
The
output of the ALU becomes the Z-bus.
The Z-bus negative-powered bus enters
data to polarity hold latches of the
registers.
The Z-bus positive-powered
bus ente.rs data to the Rand S
registers.
ALU AND SOURCE REGISTERS
•
The A and B registers supply data to
ALU.
•
ALU performs arithmetic and logical
operations.
•
The ALU output is corrected for
parity, if necessary.
The data which is supplied to the A and
the B registers by their respective
buses, is fed to the ALU where arithmet-
1-33
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