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IBM 2030 Manual Of Instruction page 309

Processing unit, field engineering

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The C counter is FULL every .25
seconds •
A latch ON in the C counter causes a
timer interrupt at the end of E-
phase.
For machines operating on 60 cycle
alternating current.
The C counter is used to keep track of
time. A 60 cycle pulse provides the
drive for this counter.
Though this
'-position counter is FULL with only 15
impulses (.25 sec), any position of this
counter that is set at the end of E-
phase will cause a timer interrupt.
The interrupt routine takes the value
in the C-counter, multiplies it by 5,
and subtracts this from the timer value.
If there is a sign change as a result of
the subtraction, an extp.rnal interrupt
is
~aken.
If no Sign change the
interrupt routine exists to I-phase for
the next instruction.
The big question
in your mind is probably, -multiply by
5?-
Remember, the value of 300 is sub-
tracted from the timer for one second of
Latches
Contro I Latc h
elapsed time.
For .25 of a second, the
value of 75 must be subtracted from the
timer.
If the C counter has only four
positions, the highest value it can
contain is 15 (1111, all positions set).
All positions of the C-counter are set
in .25 of a second.
Therefore, the full
value in the counter (15) multiplied by
5 gives the value (75) that must
be
subtracted from the timer for this
elapsed time.
The controls for the C-counter are
shown in Figure 5-23.
The governing
latch is the control latch.
This latch
must be off to allow the C counter to
run.
If the disable-timer switch is
off, the control latch will be turned on
when main storage location 51 is
addressed.
This location is addressed
when the customer desires to set the
timer to a new value.
~ith
the control
latch on, the control FF latch is set at
T4 time.
This latch controls the lines
to reset the C counter latches.
The
control FF latch turns the control latch
off at T3 time.
The control latch going
off resets the control FF latch.
C Counter
Reset
(Binary Connected)
Control FF
Control
--'T"'4 _ _ _ .., A
Drive
Interva I Timer Sw Off
Tl
Hex Add 0051
A
Allow Timer Rst
Tl
Gt C Reg to
A Bus
T3
Control FF Latch
(Not Control Latch
OR Control Latch
(Not) Ctr Full
-FL-
T2
A
A
Not T2
Figure 5-23.
Interval Timer Controls
-FF-
Drive
-FF-
Drive
-FF-
4
-FF-
5
-FF-
6
-FF-
7
Timer Update
A
Cntr Full
5-49

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