Xycom XVME-678 Manual page 97

4.7.2
Auxiliary Non-Maskable Interrupts
XVME-678/688 Manual
July 1994
Two non-maskable interrupts (ANMls) have been added to the basic IBM PCI A T architecture: the
ABORT switch and SYSFAIL (see Figure 4-10).
The IBM
PCI
A T architecture provides a mechanism to disable and enable NMls: an output to port 70H
with D7 =0 enables NMls; an output to port 70H with D7 = 1 disables NMls. This mechanism is also used
to enable and disable the ANMls. Both ANMls are implemented as latches. When the interrupt occurs
and is enabled, the latch will set. The latch remains set until the interrupt is disabled or a system reset
occurs.
SYSFAIL and the ABORT switch are mapped onto the NMI by setting bit 0 on Control Register 4 to O.
SYSFAIL and the ABORT switch are enabled by setting bit 4 of Control Register 1 to 1 and by enabling
the individual interrupt enable in Control Register 5. If bit 4 is on and at least one of the individual
enables in Control Register 5 is on, the occurrence of the interrupt event will set a latch, which remains
set until bit 4 is reset.
When the latch is set, the NMI will occur if the module NMI (bit 7 of port 70H) is enabled. The state
of these latches can be determined by checking Status Register 1 (32H). The SYSFAIL latch is bit 2 and
the ABORT switch latch is bit 3. When any of these bits is high, the corresponding latch is set.
Bit 0
of
CONREG4 = 0
}-----IS
R
J--I---IS
R
Bit 7 of Output Port 70h
IBM
AT
NMI
CONREGS_2 - Control Register 5 bit 2
Control Register 5 • I/O 3 Eh
Q~_~
_ _ _
S_T_Aru_S_l~_2~
SYSFAIL
NMI
LATCH
ABCAT
NMI
LATCH
I/O 32h
Figure 4-10. Auxiliary Non-maskable Interrupt Structure
NMI
4-25