Interrupts; Auxiliary Maskable Interrupts (Amis) - Xycom XVME-678 Manual

Chapter
4 -
Programming
4.7 INTERRUYfS
The XVME-678/688 handles interrupts on the VMEbus. In addition to the interrupts generated by the
PCI AT peripheral chips, the XVME-678/688 handles the following interrupts:
• VMEbus interrupts
• Auxiliary maskable interrupts (VMEbus interrupts; BERR, SYSF AIL, ABORT switch mapped
to IRQ1O)
• Auxiliary non-maskable interrupts (ABORT switch and SYSFAIL mapped to NMI (IOCHCK*»
All seven VMEbus interrupt levels can interrupt the XVME-678/688 (refer to Figure 4-8 on the next
page). Each VMEbus interrupt level has a separate enable bit located in Control Register 4 (3DH). When
this enable bit is set to 1, the interrupt is enabled. When the enable bit is set to 0, the interrupt is
disabled. (Refer to section 4.6.8.)
Each VMEbus interrupt line has a bit position in the AUX_INT input port (see section 4.6.2). VMEbus
interrupt level 1 corresponds to AUX_INT bit position 1. When a particular bit in AUX_INT is set, the
corresponding VMEbus interrupt is pending. The XVME-678/688 should run a VMEbus lACK cycle on
the corresponding interrupt level (refer to section 4.3.2) to satisfy the VMEbus protocol and to acquire
the status ID vector. Software should ensure the VMEbus interrupter has negated its interrupt before
leaving the ISR.
4.7.1 Auxiliary Maskable Interrupts (AMIs)
Ten maskable interrupts have been added to the basic IBM PCI AT architecture. They consist of the seven
VMEbus interrupts, BERR, SYSFAIL, and the ABORT switch (refer to Figure 4-8 on the next page).
The seven VMEbus interrupts are always mapped to IRQI0. SYSFAIL, BERR, and the ABORT switch
can be mapped to IRQ 10 or the ANMI structure. None of these three can cause interrupts on
both
IRQ 10
and the ANMI.
All seven VMEbus interrupt AMls are disabled by bit 7 of Control Register 1 (30H). Bit 0 of Control
Register 4 determines whether BERR, SYSFAIL, and the ABORT switch are mapped onto IRQI0 or the
ANMI structure.
If these interrupts are mapped onto IRQ1O, the clearing and enabling mechanism is the enable/disable bit
in Control Register 5 (see Figure 4-9 on page 4-24). For example, if an interrupt (IRQ1O) was caused by
BERR, the interrupt event is determined by reading Status Register 1. It is cleared by setting bit 0 of
Control Register 5 to O. The control bit may then be set back to 1 to re-enable.
4-22