Xycom XVME-678 Manual page 85

XVME-678/688 Manual
July 1994
If the bus error interrupt is enabled (bit 0 in Control Register 5 is set to 1) and mapped to the IOCHCK*
signal, asserting BERR has the same effect as a parity error on the I/O channel. The BERR signal is
linked into the IBM AT architecture in the same manner as the IOCHCK* signal. Bit 3 of I/O port B (I/O
address 61H) enables the IOCHCK* and BERR* signals.
When enabled, the assertion of BERR during an XVME-678/688 master cycle causes a latch to set. The
status of this latch can be detected by bit 0 of Status Register 1. If this bit is 1, the BERR latch is set and
generating an I/O channel error NMI. If this bit is 0, the latch is cleared. If the bit is 1, bit 6 of I/O port
B is set to indicate an I/O channel error. To reset the latch, set bit 3 of the AT's port B to 1. To disable
the BERR signal from causing I/O channel errors, set bit 0 of Control Register 5 to O.
All master cycles are byte-swapped during read and write operations. (Refer to Section 4.8 for more
information on byte-swapping.)
The XVME-678/688 offers a Release on Request Option (ROR) which can be selected in Control Register
6 (3FH). When ROR is selected, the XVME-678/688 keeps the bus after it makes an access until another
master requests to use the bus. This option reduces the number of arbitration cycles on the VMEbus when
there is a limited number of masters. This increases the VMEbusthroughput.
NOTE
If the bus is obtained by using bit 3 of Control Register 1 (30h), the ROR
option will not release the VMEbus until bit 3 is negated.
To change the bus request level, the XVME-678/688 must lock onto the bus. Bit 3 of Control Register
1 (30h) and bit 4 of status register 2 (33h) are used in this procedure. When bit 3 of Control Register 1
is set to 1, the VMEbus master interface requests the bus. Bit 4 of status register 2 can then be polled to
determine when the master interface has been granted ownership. When bit 4 is set to 1, the master
interface does not have ownership. When bit 4 is set to 0, the master interface has ownership. Once the
master interface gets ownership of the bus, it won't release it until bit 3 of Control Register 1 is reset by
the 80386SX.
To change the Bus Request Level of the XVME-678/688, follow the steps below:
1. Set bit 3 of Control Register 1 (30H) to 1.
2. Poll bit 4 of status register 2 (33H) and wait until it becomes O.
3. Change the Bus Request Level by writing to Control Register 6 (3FH).
4. Set bit 3 of Control Register 1 to O.
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