Vmebus Master Interface - Xycom XVME-678 Manual

Chapter
4 -
Programming
4.4 VMEBUS MASTER INTERFACE
The VMEbus master interface allows the XVME-678/688 to become a master or interrupt handler on the
VMEbus. The master interface is disabled or enabled in Control Register 3 (3CH). The master interface
is invoked whenever the CPU accesses the VMEbus Standard address space, the Short I/O address
location, or the lACK address location. All accesses over the VMEbus are through the Real Mode
Window (described in Section 4.3).
VMEbus cycles may be terminated with BERR or DTACK (see Figure 4-7). Circuitry is provided to
allow BERR detection as either an 110 channel check error or as IRQ 10. Bit 0 in Control Register 4
(3DH) determines where local bus error interrupts are mapped i{enabled. Refer to Section 4.7.1 if the
BERR signal is mapped onto IRQlO.
Circuitry inside this box is non·standard
hardware added to allow BERR detection.
All circuitry outside the box is standard IBM AT
hardware. It is shown for reference only.
r---------------------------------------
10CHCK ..
-~----a ~-----~
BERR*---a
CONREG5_0
- - - - - - I
""'---IS
Bit 0
of
STATUS 1
a~~----_r~-----------~
R
--------. -----------------------------1
Bit 3 of
- - - - 0
>---........ --------------------------Cl
R
I/O Port B
STATUS
1 =
1I032H
Bit 6
of
1/0
Port B
Q~~----------~~
110 Channel
ErrorNMI
Bit 7 of
I/O Port 70H - - - - 0
>--------------------------------------------1
Figure 4-7. BERR Mapped Onto 10CHCK*
4-12