Xycom XVME-678 Manual page 144

Appendix A - VMEbus Connector/Pin Description
Table A-I. VMEbus Signal Identification
(continued)
Signal Connector, Row: Signal Name and Description
Mnemonic Pin Number
SYSCLK 1A:1O SYSTEM CLOCK: A constant 16 MHz clock signal that
is independent of processor speed or timing. It is used for
general system timing use.
SYSFAIL* 1C:1O SYSTEM FAIL: Open-collector driven signal that
indicates that a failure has occurred in the system. It may
be generated by any module on the VMEbus.
SYSRESET* 1C:12
SYSTEM RESET: Open-collector driven signal which,
when low, will cause the system to be reset.
WRITE* 1A:14
WRITE: Three-state driven signal that specifies the data
transfer cycle in progress to be either read or written. A
high level indicates a read operation, a low level
indicates a write operation.
+5V STDBY 1B:31 +5 VDC STANDBY: This line supplies +5 VDC to
devices requiring battery backup.
+5
1A:32 +5 VDC POWER: Used by system logic circuits.
1B:32
1C:32
2B:1,13,32
+12V
1C:31
+ 12 VDC POWER: Used by system logic circuits.
-12V
1A:31
-12 VDC POWER: Used by system logic circuits.
A-4