Memory Reservation For Memory-Mapped Functions; Memory Interleaving - Intel S7000FC4UR Technical Product Specification

BIOS Initialization
During memory discovery, the BIOS keeps track of the minimum latency requirements of each
installed FBDIMM by recording relevant latency requirements from each FBDIMMs SPD data.
The BIOS then arrives at a common frequency that matches the requirements of all components
and configures both the MCH and individual FBDIMMs with that common frequency.
14.2.9

Memory Reservation for Memory-Mapped Functions

Memory address space starting at 4 GB and extending downward is reserved for various
system BIOS, chipset, and PCI memory resource requirements. The starting address of this
memory hole is controlled by the BIOS Setup PCI Memory Mapped I/O Space menu item. The
user can configure the starting address of the memory hole to the following:
1.0GB
2.0GB (default)
3.0GB
The user may wish to select a lower memory address space starting address (larger memory
hole size). This increases the amount of memory available for allocation to PCI devices.
The chipset provides the High-Memory Reclaim feature. This feature allows the BIOS to remap
the physical memory behind this memory hole back into the system memory address space
above the 4GB boundary. The BIOS always enables High-Memory Reclaim if it discovers any
installed physical memory behind (overlapping) the memory hole address space. See the
chipset technical documentation for more details regarding this Memory Mapped Configuration
Region.
Operating systems must support Physical Address Extensions (PAE) or Intel
technology to utilize memory mapped above the 4GB boundary and recapture this memory for
operating system and application use. Most operating systems support this feature. See the
relevant operating system manuals for details.
14.2.10

Memory Interleaving

In general, to optimize memory accesses, the BIOS enables Branch Interleaving. This allows
the chipset to interleave data for successive cache-lines between the autonomous branches.
Additionally, the chipset MCH also provides interleaving across logical memory devices called
ranks. A pair of single-ranked lock-stepped FBDIMMs constitutes a memory rank. Interleaving
effected between ranks allows the chipset to interleave cache-line data between participant
ranks, and the process is called Rank Interleaving.
The BIOS by default enables 4:1 Rank Interleaving, in which four ranks participate in one
cache-line access. For more details, see the chipset documentation.
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Intel® Server System S7000FC4UR
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EM64T
Revision 1.0