Bmc Messaging Interfaces - Intel S7000FC4UR Technical Product Specification

BMC Messaging Interfaces

23. BMC Messaging Interfaces
This chapter describes the supported BMC communication interfaces:
Host SMS Interface via low pin count (LPC) / keyboard controller style (KCS) interface
Host SMM interface via low pin count (LPC) / keyboard controller style (KCS) interface
Intelligent Platform Management Bus (IPMB) I
Emergency management port (EMP) using the IPMI-over-serial protocols for serial
remote access
LAN interface using the IPMI-over-LAN protocols
23.1.1 Server Management Software (SMS) Interface
The SMS interface is the BMC host interface. The BMC implements the SMS KCS interface as
described in the IPMI 2.0 specification. The BMC implements the optional Get Status / Abort
transaction on this interface. Only logical unit number (LUN) 0 is supported on this interface.
If so configured via the Set BMC Global Enables command, the BMC can generate an interrupt
requesting attention when setting the SMS_ATN bit in the status register.
The SMS_ATN bit being set indicates one or more of the following:
At least one message is in the BMC receive message queue
An event is in the event message buffer
Watchdog pre-timeout interrupt flag set
All conditions must be cleared and all BMC to SMS messages must be flushed for the
SMS_ATN bit to be cleared.
The host I/O address of the SMS interface is nominally 0CA2h – 0CA3h, but this address
assignment may be overridden. See the platform-specific information in the appendix.
The operation of the SMS interface is described in the Intelligent Platform Management
Interface Specification. See the chapter titled, "Keyboard Controller Style (KCS) Interface."
23.1.2 SMM Interface
The SMM interface is a KCS interface that is used by the BIOS when interface response time is
a concern, such as with the BIOS SMI handler. The BMC gives this interface priority over other
communication interfaces. The BMC has limits on how many back-to-back transactions it can
handle without loss in responsiveness. It must be able to handle up to 30 back-to-back
commands from the BIOS.
The BMC implements the optional Get Status / Abort transaction on this interface. Only LUN 1 is
supported on this interface.
The event message buffer is shared across SMS and SMM interfaces.
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Intel order number E18291-001
ESB2 BMC Core TPS
Revision 1.0