Intel S7000FC4UR Technical Product Specification page 164

BIOS Initialization
Bus
PCI Express* x8
PCI Express* x8
PCI Express* x8
PCI Express* x4
PCI Express* x4
PCI Express* x4
14.3.3.1 Resource Allocation
The BIOS assigns PCI bus numbers and base addresses for I/O, prefetch memory, and non-
prefetch memory resources in ascending order of bus number, device number, and function
number.
14.3.3.1.1 PCI Express* Configuration Space
PCI Express* configuration space is assigned starting at the top of lower memory (HECBASE).
The user can select the starting address of this PCI Memory Mapped I/O Space in BIOS Setup
as described in Section 14.2.9.
PCI memory resources are assigned starting at the bottom of this memory hole upwards to the
upper boundary of PCI Express* configuration space at 0xFE000000.
14.3.3.2 Interrupt Allocation
The BIOS assigns interrupts for devices connected to the North Bridge to the ESB2 PXH I/O
Advanced Programmable Interrupt Controller (IOAPIC) [0..6]. Interrupts for ESB2 internal
devices and devices connected to the ESB2 are assigned to the ICH IOAPIC [0..7].
14.3.3.2.1 Interrupt Delivery
Interrupt delivery is via PCI Express* default ASSERTx/DEASSERTx messages delivered to the
appropriate I/OAPIC unit. Final delivery to the CPU complex is via Programmable Interrupt
Controller (PIC) by default or I/OAPIC by operating system switch. The BIOS does not support
Message Signaled Interrupts (MSI) or user interrupt selection.
14.3.3.3 "Fake MSI" Support
"Fake MSI" is enabled only for the BnB PCI-Express ports 4 though 7. The respective slots
using these ports would be benefited by using "Fake MSI".
14.3.3.4 Option ROM Support
BIOS Setup options are provided to allow for user control of Option ROM Enable/Disable for
onboard devices and adapters installed in PCI Express* slots. This allows for utilization control
over limited Legacy Shadow RAM region resources in the C000h and D000h segments. In most
cases, Legacy Option ROM execution is not required unless its device is an Initial Program
Load (IPL) device for a legacy operating system.
142
PCI Device
Slot 2
Slot 3
Slot 4
Slot 5
Slot 6
Slot 7
Intel order number E18291-001
ESB2 BMC Core TPS
Comments
Hot-plug Capable
Revision 1.0