Smbus Block Diagram; Figure 9. Smbus Block Diagram - Intel S7000FC4UR Technical Product Specification

Intel® Server System S7000FC4UR TPS
3.2.2

SMBus Block Diagram

Rear Video Front Panel
Connector Connector
VID_DDC_*_REAR VID_DDC_*_FRONT
5V 5V
3.3V
SMBus SMBus
Translation Translation
VGADDCDAT/
3.3V
VGADDCCLK
CRT2DDCDAT/
3.3V
CRT2DDCCLK
VID_DVO_DDC_*
RN50
GPIO[6:5]
FLBSD0/FLBSINTEX0 3V3STBY
SMBD0/SMBCLK0
(TCO)
FLBSD1/FLBSINTEX1 3V3STBY
SMBD1/SMBCLK1
0-ohm
(empty)
SMBD2/SMBCLK2
3V3STBY
BMC
0-ohm
(empty)
3V3STBY
SMBD4/SMBCLK4
0-ohm
3V3STBY
SMBD3/SMBCLK3
0-ohm
SMLink0=CLK
SMLink1=Data
SMLINK0/1 (Slave) 3V3STBY
Addr 0x44
SMB_SMLINK_3V3SB_*
ICH6
SMBCLK/SMBDATA
3V3STBY
(Master)
Addr 0x44
3V3STBY
Repeater
PCA9515
0-ohm
PEXH
SDTA/SCLK 3.3V
(0xC4)
3.3V
HPDTA/HPCLK
(PCIE HP) Not used
ESB2
Revision 1.0
S7000FC4UR SMBus Block Diagram
RMM2/ASMI Dynamic Bus Addressing for PCIe Slots (i.e. PCIe
slots support SMBus address resolution protocol)
BMC
FPGA
IPMB
0x30 (MS)
0x26
0x32 (SL)
Tyco 8H Plug 120 pins
(P/N: 179031-5)
Tyco 5H Receptacle 120 pins
(P/N: 177983-5)
FRU LM75
Note: LM75 is a
Addr: 0x96 placeholder
Addr: 0xA8
Intel IO Riser
SMB_PCIE_3V3SB_*
Note: PCIe SMBus is
0-ohm
NOT supported. 0-ohm
(empty)
option is just a provision
SMB_CPU_3V3_*
and not a supported
feature.
Baseboard
IPMB HDR
CPU # 4
EEPROM
(SMB Addr: AE)
Note: ESB2 BMC does not
act as a SMBus ARP
Note: CPU_PECI_IO is a
master.
PECI and not a SMBus
SMB_IPMB_*
Level
Intel® SR 4851HW4 Front Panel
Shift
5VSTBY
SMB_SAS_3V3SB_*
USB HUB
USB20H04D
FRU
Addr: 0x5A
BMC GPIO
LM94 Addr: 0xA6
Expander
(2)
LM75
PCA9555
(Addr: 0x58)
Addr: 0x98
(Addr: 0x40) SMBus
Isolation
Empty
LM94
AT24C64
Note: FP Board USB HUB & EEPROM
SMBus addresses need to be changed if
(1)
the SMBus isolation is populated.
FRU
ADT7490
(Addr: 0x5C)
(Addr: 0xA0)
3V3STBY Repeater
PECI
PCA9515
Device
(Addr: 0x5A)
SMB_BB_SENSOR_3V3SB_*
3V3STBY
0-ohm
Note: SMB_SMLINK_3V3SB_* is not
connected to any devices in the
default configuration. If connected to
PC87427 (SIO3)
TMP141
a SMBus, it will be connected to only
SensorPath
one SMBus and so both the 0-ohms
(Addr: 0xD8)
will not be stuffed at the same time.
Ambient Temp
If it is connected to ICH6 SMBCLK/
(Addr: 0x02)
DATA, SMLINK0/1 will have to
change it's slave address to 0x88.
PCIe HP
Controller
Advanced
DB1900G
(TPS2363)
I2C POST
(0xD4)
Addr: 0x8C
Card
Slot # 1 & 2
PCIE
(Addr: 0xE0,
3V3
0x70, 0x76) 0-ohm
(empty) 0-ohm
(empty) 3.3V
SMBus
Isolation
SMB_CLK_IO_3V3SB_*
3.3V
SMBus
CK410B
Isolation
(0xD2)
EMPTY
SAS_Riser
SSMBDAT/SSMBCLK
SMB_SAS_3V3SB_*
(Addr: 0xE0)
SES IBBU
Header
SMBus Header
89HPES24N3A
Addr:
Isolation
0x14, 0x16
(Empty)
SAS RAID (PCIe Expander)
FRU
PCIe Hot-Plug
Slot # 1 & 2
Addr: 0xA8 DIMM
PCIE_HP12_SMB*
I/O Port
Addr: 0xA2
MSMBDAT/MSMBCLK
(PCA9555)
SAS I2C1
Bootstrap
Addr: 0x40
Controller EEPROM PCA9543
Addr: 0xA8
89HPES24N3A Slave SMBus
SMB Switch
I2C0 supports ARP (SMBus
address resolution protocol)
SMB_CHIPSET_3V3_*
SMB_MEM_3V3_*

Figure 9. SMBus Block Diagram

3V3
Note: CPU SMBus is NOT supported. 0-ohm
option is just a provision and not a supported
feature. CPU1 SMBus address conflicts with SAS
Riser FRU SMBus address if the CPU SMBus is
connected for debugging.
CPU # 3
CPU # 2 CPU # 1
EEPROM
EEPROM EEPROM
(SMB Addr: AC) (SMB Addr: A8)
(SMB Addr: AA)
2.5" SAS Backplane
3V3STBY OEM (0x9E)
SMBus
Translation Header (0xA6)
SMBus
SDA2/SCL2
5VSTBY Isolation
INTEL LCD 3V3 SES
Module SDA1/SCL1 Header
VSC410
Addr: 0x22 PWR: 3V3
FRU
Addr: 0xAC SDA3/SCL3
NON INTEL
VSC410
USB Temp
LCD Module
Addr: 0x90
EEPOM 3V3
Addr: 0xDA Fan fail LEDs
(0xA0) Fan presence, ,
SMBus
Empty System Type ,
Isolation
3V3STBY IO Expander
PCA9554
Note: SAS Backplane FRU SMBus
Addr: 0x42
address needs to be changed if the
SMBus isolation is populated.
SMB_SYS_BRD_*
Power Supply #1
3V3STBY
FRU
Addr: 0xAC
SMB_SYS_PWR_*
3V3STBY
PSMI
Addr: 0xB0
AT24C02 (FRU)
Addr: 0xAA
Power Dist Board
PSMI
Addr: 0xB2
DB1200G
DB1900G
FRU
(0xDE)
(0xD8) Addr: 0xAE
FSB
FBD, Branch0
3V3
3V3
Power Supply #2
SMB_CLK_IO_3V3_*
0-ohm
0-ohm
(empty)
3V3 (empty)
3V3
3V3
DB1900G
XDP2
(Chipset)
(0xDA)
SMBus
FBD, Branch1
Master Only
3V3
XDP1 (CPUs)
SMBus
SSMBDAT/SSMBCLK
(Addr: 0xE2) Master Only
89HPES24N3A
(PCIe Expander)
Slot # 3 & 4
89HPES24N3A Slave SMBus
supports ARP (SMBus
address resolution protocol)
Main Board Server Management
Rev 2.1
1/26/07
3V3
DIMM D1
DIMM A1
SEEPROM 0xA0
SEEPROM 0xA0
AMB 0xB0
AMB 0xB0
DIMM D2
DIMM A2
SEEPROM 0xA2
SEEPROM 0xA2
AMB 0xB2
AMB 0xB2
DIMM D3
DIMM A3
SEEPROM 0xA4
SEEPROM 0xA4
AMB 0xB4
AMB 0xB4
DIMM D4
DIMM A4
SEEPROM 0xA6
SEEPROM 0xA6
AMB 0xB6
AMB 0xB6
DIMM D5
DIMM A5
SEEPROM 0xA8
SEEPROM 0xA8
3V3
3V3
AMB 0xB8
AMB 0xB8
DIMM D6
DIMM A6
SEEPROM 0xAA
SEEPROM 0xAA
AMB 0xBA
AMB 0xBA
DIMM D7
DIMM A7
SEEPROM 0xAC
SEEPROM 0xAC
AMB 0xBC
AMB 0xBC
DIMM D8
DIMM A8
SEEPROM 0xAE
SEEPROM 0xAE
AMB 0xBE
AMB 0xBE
FRU: Addr A0
FRU: Addr A4
NE1617
NE1617
Temp Sensor
Temp Sensor
(Addr: 0x34) (Addr: 0x30)
DIMM B1 DIMM C1
SEEPROM 0xA0
SEEPROM 0xA0
AMB 0xB0
AMB 0xB0
DIMM B2
DIMM C2
SEEPROM 0xA2
SEEPROM 0xA2
AMB 0xB2 AMB 0xB2
DIMM B3
DIMM C3
SEEPROM 0xA4
SEEPROM 0xA4
AMB 0xB4 AMB 0xB4
DIMM B4 DIMM C4
SEEPROM 0xA6 SEEPROM 0xA6
AMB 0xB6
AMB 0xB6
DIMM B5 DIMM C5
SEEPROM 0xA8 SEEPROM 0xA8
AMB 0xB8 AMB 0xB8
DIMM B6 DIMM C6
SEEPROM 0xAA
SEEPROM 0xAA
AMB 0xBA
AMB 0xBA
DIMM B7 DIMM C7
SEEPROM 0xAC
SEEPROM 0xAC
AMB 0xBC AMB 0xBC
DIMM B8
DIMM C8
SEEPROM 0xAE SEEPROM 0xAE
AMB 0xBE AMB 0xBE
FRU: Addr A6 FRU: Addr A2
NE1617
NE1617
Temp Sensor Temp Sensor
(Addr: 0x9C)
(Addr: 0x98)
3.3V 3.3V
SPD1SMBDATA/CLK SPD2SMBDATA/CLK
(Master SPD, 100KHz) (Master SPD, 100KHz)
3.3V
3.3V
SPD0SMBDATA/CLK SPD3SMBDATA/CLK
(Master SPD, 100KHz)
(Master SPD, 100KHz)
3.3V
CFGSMBDATA/CFGSMBCLK Not used
CNB PCIE
(Slave, 100KHz, 0xC0)
HP SMbus
Clarksboro
35