Direct Cache Access (Dca) - Intel S7000FC4UR Technical Product Specification

Intel® Server System S7000FC4UR TPS
14.1.14.1 Limitations
The "Fake MSI" scheme can only be used by I/O devices that support MSI capability. All
PCI Express* devices must support either MSI or MSI-X.
The "Fake MSI" scheme cannot be used with a device that supports MSI-X
supports MSI-X only and does not support MSI.
The "Fake MSI" scheme can be used with MSI capable devices only. It cannot be used
with a device that only supports MSI-X.
The I/OxAPIC interrupt used for "Fake MSI" cannot be shared because MSI is an edge-
triggered mechanism and sharing results in loss of interrupts.
Even if the I/O device is multiple-message capable, firmware must program the device to
allocate one vector only. The "Fake MSI" scheme cannot support MSI multiple
messages. This is required to ensure that the device-function does not modify any bits of
the message data field.
Each I/O device that intends to use the "Fake MSI" scheme should be programmed to a
unique MSI data value corresponding to a unique I/OxAPIC input. The MSI address
remains the same as we are targeting the PAR of the ESB2 I/OxAPIC.
If the I/O device generates interrupts for multiple internal events, the device driver ISR
must check for all internal events on each interrupt
possible.
In case of multi-function devices, the "Fake MSI" scheme can be used to support up to
four functions only. This is because interrupt routing of devices using the "Fake MSI"
scheme are exposed to the operating system using MPS1.4 or _PRT table; these
firmware tables are limited to four unique interrupts per device as required by the PCI
Specification.
14.1.15

Direct Cache Access (DCA)

Direct cache access (DCA) is a component of Intel
as described in Section 20.1.
The DCA mechanism is a system-level protocol in a multi-processor system to improve I/O
network performance, thereby resulting in higher system performance. The basic idea is to
minimize cache misses when a demand read is executed. This is accomplished by placing the
data from the I/O devices directly into CPU cache through hints to the processor to perform a
data prefetch and install it in its local caches.
The BIOS enables DCA by default.
1
MSI-X requires BAR registers to be initialized to locate the MSI-X table in MMIO space. Since legacy operating
systems could potentially reconfigure the device and its BARs, in the case of "Fake MSI", there is a risk of losing the
MSI-X programming done by the BIOS.
2
The concern here is that a device driver written with level triggered semantics in mind may dismiss the interrupt with
processing all the internal events associated with the interrupt because it is assured that the interrupt will be
reasserted as long as internal events are pending.
Revision 1.0
2
. Otherwise, overrun situations are
®
I/O Acceleration Technology (Intel
BIOS Initialization
1
The device
®
I/OAT)
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