Intel S7000FC4UR Technical Product Specification page 151

Intel® Server System S7000FC4UR TPS
14.2.14.2 Memory BIST (MemBIST)
The BIOS enables the MemBIST hardware engine during POST memory initialization on every
boot. The MemBIST hardware engine isolates failed FBDIMMs. The BIOS then completes the
following actions:
Marks those FBDIMMs as failed
Takes them off-line
Displays an error message in the POST Error Manager
14.2.14.3 FBDIMM Channel Failure
The chipset supports FBD Fail-over mode operation for both southbound and northbound
interfaces. For southbound lanes, it supports 10-bit lanes with fail-over to nine lanes. For
northbound lanes, it supports 14-bit lanes with fail-over to 13 lanes (14-lane fail-over mode).
14.2.14.3.1 POST
During POST, failed lanes are detected during channel initialization after reset. If the chipset
detects a lane has failed during channel initialization, it configures the interface for fail-over
mode.
In general, when a fatal link failure occurs, the BIOS disables all FBDIMMs on that link. If all
FBDIMMs are present on the same faulty link, the BIOS generates POST code 0xE1 to indicate
that the system has no usable memory, and then halt the system.
14.2.14.3.2 Runtime
During runtime, failed lanes are detected during FBDIMM fast reset that can be triggered by
alerts or recoverable memory sub-system errors (e.g. multi-bit ECC errors). If the chipset
detects a lane has failed during fast reset, it configures the interface for fail-over mode.
If a fatal link failure occurs during normal operation at runtime (after POST), the BIOS signals a
fatal error. It then performs policies related to fatal error handling.
14.2.14.4 Memory ECC Errors
Memory ECC errors are handled by the BIOS at runtime.
14.2.14.4.1 Error Counters and Thresholds
The BIOS uses error counters on the chipset and internal software counters to track the number
of runtime ECC correctable errors. The chipset increments these counter registers when an
error occurs. The count also decays at a given rate programmable by the BIOS. Due to the
particular nature of the counters, they are termed Leaky Bucket Counter (LBC) registers.
14.2.14.4.1.1 LBC Registers
The LBC registers provide a measurement of the frequency of errors. The BIOS configures and
uses the leaky bucket counters and the decay rate such that it can be notified of a failing
Revision 1.0
BIOS Initialization
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