System Memory Ras And Bus Error Monitoring - Intel S7000FC4UR Technical Product Specification

BMC Functional Specifications

22.20 System Memory RAS and Bus Error Monitoring

System memory and bus error monitoring is done by the system BIOS. Early in the startup boot
process, the BIOS checks the chipset for any memory errors. The BIOS updates the status of
RAS configuration at startup and later at run time. BMC monitors and logs SEL events based on
the SDR definitions. In addition, the BIOS help the BMC maintain the current DIMM presence
and failure state and current memory RAS configuration, such as memory sparing and
mirroring.
Support is provided for monitoring errors on system buses, such as front side bus (FSB) errors
and PCI bus errors. The BIOS monitors these and generates critical interrupt sensor SEL
events when an error is detected.
22.21 BMC Self Test
The BMC performs tests as part of its initialization. If a failure is determined, such as a corrupt
BMC SDR, then the BMC stores the error internally. BMC or BMC sub-system failures detected
during regular BMC operation may also be stored internally. Two commands may be used to
retrieve the detected errors. The IPMI 2.0 Get Self Test Results command can be used to return
the first error detected. The Read Self Test command can be used to sequentially read all the
accumulated self test errors.
22.22 Field Replaceable Unit (FRU) / Fault LED Control
Several sets of FRU / POST / fault LEDs are supported. Some LEDs are owned by the BMC
and some by the BIOS.
The BMC owns control of the following FRU / fault LEDs:
Fan fault LEDs – A fan fault LED is associated with each fan. The BMC lights a fan fault
LED if the associated fan tach sensor has a lower critical threshold event status
asserted. Fan tach sensors are manual rearm sensors, therefore once the lower critical
threshold is crossed, the LED remains lit until the sensor is rearmed. These sensors are
rearmed at system DC power-on and system reset.
CPU fault LEDs – A CPU fault LED is associated with each processor slot. The BMC
lights a CPU fault LED when the associated processor status sensor has either the
configuration error or processor disabled offset asserted. Processor status sensors are
manual rearm sensors, so if either of these offsets is asserted, the LED remains lit until
the sensor is rearmed. These sensors are not rearmed at system DC power-on or
system reset.
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Intel order number E18291-001
ESB2 BMC Core TPS
Revision 1.0