Bmc Functional Specifications - Intel S7000FC4UR Technical Product Specification

BMC Functional Specifications

22. BMC Functional Specifications
22.1 Power System
The ESB2 BMC is not the power control path, but it can block power control actions that are
caused from front panel power button presses or chipset-initiated power state changes. It can
generate power state changes by simulating a front panel power button press. It monitors both
the requested power state from the chipset and the power good state.
22.1.1 Power Supply Interface Signals
The ICH controls the POWER_ON signal. It connects to the chassis power sub-system and is
used to request power state changes (asserted = request power on). The POWER_GOOD
signal from the chassis power sub-system indicates the current power state (asserted = power
is on).
To turn the system on, the BMC asserts the BMC_FP_POWER signal and waits for the
POWER_GOOD signal to assert in response, indicating that DC power is on.
The POWER_GOOD signal is normally asserted within 1.5 seconds, but the timeout interval can
be set longer to add flexibility in manufacturing test environments. The POWER_GOOD signal
must remain stable and not glitch when being asserted. The BMC uses the state of the
POWER_GOOD signal (indirectly monitored through another signal available to the BMC) to
monitor whether the power supply is on and operational, and to confirm whether the system
power state matches the intended system on / off power state that was commanded with the
POWER_ON signal.
22.1.2 Power-Good Dropout
De-assertion of the POWER_GOOD signal generates an interrupt that the BMC uses to detect
either power sub-system failure or loss of AC power. The BMC performs the power fault
analysis according to section 22.19.4 to determine the cause of the POWER_GOOD signal
dropout. A power-good dropout is defined as the POWER_GOOD signal de-asserting when the
system should be in the DC power-on state as determined by the state of the POWER_ON
signal. If the BMC detects a power-good dropout, the following occurs:
The BMC powers down the system.
The BMC asserts the Power Unit Failure offset of the Power Unit sensor and logs a SEL
event. See section 22.19.1.5.
The BMC generates a beep code for a Power Fault. See Table 10.
The BMC waits 10 seconds. If the power state retention feature is configured to power
on the server after an AC loss, it attempts to power up the server. This is the case in
which either AC dropped out momentarily, but not long enough to reset the BMC, or the
power sub-system had a momentary failure that the BMC could not differentiate from a
momentary AC loss.
The BMC responds to the power loss interrupt within 1-2 ms if it is in operational mode. The
BMC does not respond to a power-good dropout if it is in firmware transfer mode.
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Intel order number E18291-001
ESB2 BMC Core TPS
Revision 1.0