Intel S7000FC4UR Technical Product Specification page 249

Intel® Server System S7000FC4UR TPS
19.2.2.4 PCI Express* Errors
The server system supports a PCI Express*-based topology with all PCI devices downstream
from the root ports. PCI Express devices report errors with an in-band messaging scheme
based on these categories:
Uncorrectable, fatal errors signaled with an ERR_FATAL message.
Uncorrectable, non-fatal errors signaled with an ERR_NONFATAL message.
Correctable errors signaled with an ERR_COR message.
19.2.2.4.1 Legacy Error Reporting Scheme
The BIOS supports a legacy error reporting scheme based on SERR and PERR reporting only.
The BIOS configures all PCI Express* root ports and downstream devices such that all PCI
Express uncorrectable fatal and uncorrectable non-fatal error messages are simultaneously
reported as SERR in the standard configuration space PCI Status register SERR reporting bit
for the device. In other words, fatal and non-fatal error messages are both considered critical
errors requiring a system halt or reset to provide containment.
19.2.2.4.1.1 Error-handling Algorithm
The BIOS error-handling algorithm scans from the chipset PCI Express* root ports recursively
downstream through all bridges identifying if any downstream device has flagged an SERR or
PERR event. The handler logs a SEL entry for each PCI device reporting the error using the
IPMI Critical Interrupt SERR or PERR sensor offset as described in Section 19.2.7. Thus, the
BIOS handler reports a chain of error events starting with the highest-level device reporting an
error and proceeding through all intermediate reporting agents (PCI bridge devices) to the
lowest level device reporting the error.
The BIOS does not report PCI Express* errors flagged in either the baseline capability structure
or the optional Advanced Error Reporting (AER) structure directly as the Intelligent Platform
Management Interface Specification, Version 2.0, Intel Corporation provides no support for
reporting PCI Express* errors. Any PCI Express uncorrectable, fatal or uncorrectable, non-fatal
errors are propagated to SERR so they are captured by our legacy error handler.
19.2.2.4.2 Parity Error Reporting
Parity error reporting is a legacy concept based on parallel bus implementations in the PCI
Local Bus Specification. PCI Express* is based on CRC protected, serial communications
therefore the entire concept of parity error reporting is invalid. Consequently, the BIOS is not
expected to encounter any parity error events directly on PCI Express bus topologies.
One case in which a PCI parity error may be relevant in a PCI Express system is in the event of
an embedded traditional PCI device or PCI-X* device located behind a PCI Express to PCI or
PCI-X bridge device. In this event, the downstream PCI / PCI-X device reports a PERR event,
and then the PCI Express bridge device converts the signal into an uncorrectable error
message on the primary interface of the bridge.
Revision 1.0
BIOS Error Handling
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