Figure 71. Hsc Interface Routing; Table 105. I 2 C Bus Assignements; Hot-Swap Controller (Hsc) Architecture - Intel S7000FC4UR Technical Product Specification

Intel® Server System S7000FC4UR

28. Hot-Swap Controller (HSC) Architecture

The HSC uses a VSC410* SAF-TE enclosure processor (SEP). This microcontroller employs a
v3000 RISC CPU, 8 KB of internal SRAM, GPIO, SGPIO, two general purpose UARTs, one
2
SPI, and four I C compatible interfaces.
* If present, SGPIO is disconnected.
** If present, I2C3 is disconnected.
28.1.1 I C Interfaces
2
The VSC410 supports four I
configured in firmware to operate at 100 KHz. Optional support functions, such as I
cleanups, can be configured in firmware.
I C Bus Number
2
I2C0
I2C1
I2C2
I2C3
28.1.2 Serial Peripheral Interface (SPI)
The VSC410 SPI accesses operational code in a separate SPI-compatible EEPROM device.
This interface is private and can only be accessed by the HSC to retrieve or update firmware.
Revision 1.0

Figure 71. HSC Interface Routing

2
C compatible serial interfaces. These multi-master interfaces are
2
Table 105. I C Bus Assignements
Connection Protocol
Reserved
2
Master / slave I C (private bus)
IPMB
2
SES2-over-I C, SAFTE
Hot-Swap Controller (HSC) Architecture
Connected Device(s)
None
Temperature sensor, NV/FRU EEPROM
Baseboard management controller
Host bus adapter
2
C bus
301