Intel S7000FC4UR Technical Product Specification page 42

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Main Board
After CPU and VTT VRs are enabled, as well as any memory riser presence signal
asserted, a global VR enable is asserted for memory risers, SAS backpanel, and SAS
Riser. An additional output for IO Riser power enable will be asserted at the same time
as the other adapters in the system.
A signal internal to the PLD representing a system-wide pwrgd signal will be asserted
once all FRU pwrgd signals are asserted. This signal is inverted and used to enable
clocks. The system powergood is delayed 100ms before the PLD asserts an output for
the SYS_PWRGD_PLD signal.
2.2.18.2
Shifty Bus
The shifty bus provides a way to serially communicate status information to the BMC (Enterprise
Southbridge 2). The BMC will assert a signal that will latch 27 bits of system status information
present in the PLD. Then a clock signal (~1MHz), generated from the BMC, is used to
synchronize a bit banging process that will transfer the information. This process will be
repeated on a regular interval for the BMC to track system status.
The shifty bus will also ensure locking of shifty bus state at the moment failure is detected by
the PLD. Locking is required because regularly scheduled BMC reads of the shifty bus are not
frequent enough and may not allow for accurate failure detection. This will allow the BMC to
identify the origin of failure within the system without capturing subsequent failures. CPU/FRU
failure will be determined at falling edge of pwrgd inputs. Locking of shifty vector will be
determined by the setting of a dirty bit. Once the dirty bit has been set no change in status of
shifty vector bits will be recorded. The once the BMC has performed its scheduled shifty read, it
is responsible for recognizing the failure status, logging, and shutting down system. The shifty
dirty bit will not be cleared until a subsequent shifty bus read while in S5 (or AC cycle).
2.2.18.3
PCI-Express* Hot-plug:
The main board PLD will implement delay functions for PCI Express hot plug functionality:
100ms timer delay for the 3.3V powergood signal from the Texas Instruments* TPS2363
going to each HP-enabled PCI-Express* slot (1-4).
Generate a 100ms delayed enable (based on slot's 3.3V STBY rail) to the hot-plug
isolation logic for slot SMB and wake signals
2.2.18.4
Power Safe Monitoring
Power Safe Monitoring will monitor power supply status and utilization levels with respect to
circuit break type setting to determine when a when a PS non-redundancy bit (shifty bus) should
be asserted for reading by the BMC. The BMC will then be responsible for communicating with
LM94 controllers to throttle CPUs when appropriate.
PS non-redundancy will be enabled under following conditions:
(Both PS Present AND ((CB_Type=Japan/Brazil AND Util = 37%) OR (CB_Type = Not
Japan/Brazil AND Util = 45%))
OR
20
Intel order number E18291-001
Intel® Server System S7000FC4UR TPS
Revision 1.0

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