Resets; Figure 17. Sas Backplane Reset And Power Good Block Diagram; Table 15. I 2 C* Local Bus Addresses; Table 16. Global I C* Bus Addresses (Ipm Bus) - Intel S7000FC4UR Technical Product Specification

SAS Backplane
7.3.9.8 I C* Addresses
2
2
Two I C* devices and their addresses are listed in Table 15 and one in Table 16.
Device
AT24C64*
DS75*
Device
VSC410*
Device
PCA9554*
7.3.10

Resets

The principal reset for logic on the SAS backplane is supplied by the PCI_RST_BP_N signal
from the server board via the 100-pin connector
The PCA9554* device being used to control the fans, has an internal power-on reset that
configures all its I/O pins as inputs.
See the diagram below for reset flow.

Figure 17. SAS Backplane Reset and Power Good Block Diagram

66
2
Table 15. I C* Local Bus Addresses
Address Bus
0xAC VSC local bus
0x90 VSC local bus
2
Table 16. Global I C* bus Addresses (IPM Bus)
Address Bus
NA IPMB system interface
2
Table 17. I C* I/O Bus Addresses
Address
0x42 SMB_SYS_PWR_SDA/SCL
Description
Private SAS backplane FRU EEPROM
Private SAS backplane temperature sensor
VSC410* controller public IPMB bus
Bus
Micro controller public I/O bus
Intel® Server System S7000FC4UR
Description
Description
Revision 1.0