Table 76. Smbios Type 7 Structure - Cache Information - Intel S7000FC4UR Technical Product Specification

BIOS Role in Server Management
Offset Name
22h Part Number
23h Core Count
24h Core Enabled
25h Thread Count
26h Processor
Characteristics
18.5.3.6 Type 7 Structure — Cache Information
The SMBIOS Type 7 structure describes the attributes of the processor cache device(s) in the
server. The BIOS dynamically creates one structure per cache device present in the server. For
example, the BIOS creates six Type 7 structures if two processors are installed each supporting
three levels of cache.
Offset Name
00h Type
01h Length
02h Handle
04h Socket
Designation
05h Cache
Configuration
214
Length
Byte String
Byte Varies
Byte Varies
Byte Varies
Word Bit Field
Table 76. SMBIOS Type 7 Structure — Cache Information
Length
Byte 7
Byte 13h
Word Varies
Byte String
Word Varies
Intel order number E18291-001
Value
String number for the part number of this
processor. This value is set by the
manufacturer and normally not changeable.
Number of cores per processor socket. If
the value is unknown, the field is set to 0.
See the System Management BIOS
Reference Specification, Version 2.5,
Section 3.3.5.6 for more information.
Number of enabled cores per processor
socket. If the value is unknown, the field is
set 0. See the System Management BIOS
Reference Specification, Version 2.5,
Section 3.3.5.7 for more information.
Number of threads per processor socket. If
the value is unknown, the field is set to 0.
See the System Management BIOS
Reference Specification, Version 2.5,
Section 3.3.5.8 for more information.
Defines which functions the processor
supports.
Value
Cache information indicator.
String number for Reference Designation
Same as associated processor
Bits 15:10
0 = Reserved
Bits 9:8
00b = Write through
01b = Write back
10b = Varies with memory address
11b = Unknown
Bit 7
0b = Disabled at boot time
1b = Enabled at boot time
Bits 6:5
00b = Internal
Bit 4
ESB2 BMC Core TPS
Description
Description
Revision 1.0