Memory Sizing And Configuration; Support For Mixed-Speed Memory Modules - Intel S7000FC4UR Technical Product Specification

Intel® Server System S7000FC4UR TPS
14.2.7

Memory Sizing and Configuration

The BIOS supports various memory module sizes and configurations. These combinations of
sizes and configurations are valid only for FBDIMMs approved by Intel. The BIOS reads the
Serial Presence Detect (SPD) SEEPROMs on each installed FBDIMM to determine the
supported size and timing characteristics.
The memory-sizing algorithm then determines the cumulative size of each FBDIMM rank. The
BIOS programs the MCH accordingly, such that the range of memory accessible from the
processor is mapped into the correct FBDIMM or set of FBDIMMs.
The minimum memory configuration is 512MB for single-channel mode and 1024MB for dual-
channel mode. All four channels support up to thirty-two DIMM ranks.
14.2.8

Support for Mixed-Speed Memory Modules

The BIOS supports memory modules of mixed speed by automatic selection of the highest
common frequency of all memory modules (FBDIMM). This section describes the expected
outcome on installation of FBDIMMs of different frequencies.
14.2.8.1 FBDIMM Characteristics
To program a FBDIMM to function correctly for a given frequency, the BIOS queries each
FBDIMMs Serial Presence Detect (SPD) data store. The SPD contains the frequency
characteristics of the FBDIMM, which are measured in terms of the following parameters:
CAS Latency (CL)
Common clock frequency
Additive Latency (AL)
Buffer Read Delay (BRD)
The CAS latency and the additive latency are configurable parameters detected by the BIOS by
reading the SPD data of the FBDIMMs. The BRD is the average inherent delay that is caused
by the finite time that the FBDIMM Advanced Memory Buffer (AMB) consumes in buffering the
data read from the individual DRAM devices on the module before forwarding data on the
Northbound or Southbound path.
14.2.8.2 Host Frequency and Gear Ratio
The host frequency is the speed of the memory interface of the chipset. This frequency
determines the speed at which the chipset completes a memory transaction. The gear ratio
determines the relative speed between the processor interface and the memory interface.
The BIOS supports the following two frequencies:
533 MHz
667 MHz
The BIOS automatically selects and configures the host frequency and gear ratio.
Revision 1.0
BIOS Initialization
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