Intel® Server System S7000FC4UR
The BIOS runtime error handling is identical regardless of whether Intel
Technology is enabled. Operating system error handling is performed only by the primary
operating system. The guest operating system(s) are not exposed to any error conditions.
Note: If the Setup options are changed to enable or disable the Intel
Setting in the processor, the user must be fully powered off and powered back on again before
the changes take effect.
"Fake MSI" Support
In PCI compatible INTx mode, the chipset supports a maximum of four unique interrupts. If more
than four unique interrupts are used by devices behind the chipset root ports, it could result in a
potential interrupt scaling problem due to sharing of interrupts. On a platform that supports eight
processor cores, the configuration allows for interrupt distribution to all eight cores.
Since the available number of unique interrupts (4) for this system is less than the number of
available cores, the system cannot take advantage of all the available cores for interrupt
distribution. The chipsets provides an interrupt scaling feature called "Fake MSI" to mitigate this
All PCI Express* devices must support MSI (Message Signaled Interrupt). In this scheme, the
device causes an interrupt by writing the value of the MSI data register to the address in the
MSI address register. The resulting memory write transaction is translated through chipset logic
into an interrupt transaction for the appropriate target processor core(s). The MSI scheme
requires support in the operating systems, which is not widely available in available operating
systems. The "Fake MSI" scheme allows PCI Express devices running on a legacy operating
system to use the MSI mechanism to generate INTx compatible interrupts. This is accomplished
by targeting the MSI memory write to an I/OxAPIC.
Under the "Fake MSI" scheme, PCI Express devices are programmed to enable MSI
functionality, and given a write-path directly to the pin assertion register (PAR) of an I/OxAPIC
already present in the platform. The targeted I/OxAPIC now generates an APIC interrupt
message in response to a memory write to the PAR, thus providing equivalent functionality to a
virtual (edge-triggered) wire between the PCI Express endpoint and the I/OxAPIC. The chipsets
ensure that PCI ordering rules are maintained for the "Fake MSI" memory write.
When Fake MSI is enabled, the PCI Express devices generate a memory transaction with an
address equal to I/OxAPIC_MEM_BAR + 0x20 (PAR) and a 32-bit data equal to the interrupt
vector number corresponding to the device. This information is stored in the device's MSI
address and data registers, and would be initialized by the system firmware (BIOS) prior to
booting a non-MSI aware operating system.