AGFA Avantra 36/44 Service Manual page 97

Avantra 36/44 Service Manual
3.2.3.15 DSP Micro-controller Test Descriptions
The following list describes the tests performed on the DSP micro-controller during
the boot sequence:
• RAM Test– since the DSP runs out of RAM, it is not useful to run a check-
sum on the code. If the DSP runs, the ROM is OK. If the external RAM is
included, the software runs a march test and an address as data memory
test on the external memory.
• Port Test –the hardware loops back one bit from the DSP output port to
the DSP input port. The software sets the bit high and verifies that it is
high on the input. Then the software sets the bit low and verifies that it is
low on the input port.
• Spinner Verify Test –applies a short burst to the spinner motor and veri-
fies that the expected change in the spinner count value was correct. This
verifies that the spinner encoder was connected. It also confirms that the
spinner data input port was at least minimally functional before spinner
power-up is attempted.
• SPI Communications Verify– the DSP SPI line connects the output port of
the DSP to the DEC and the DIAG processor. At boot time the software
sets this signal low. When the first stage of the diagnostics are complete,
the software sets the DSP SPI signal high to indicate that it is ready for
commands from the DIAG. The DIAG sends a command packet to the
DSP to echo the data in the packet. This verifies the SPI communications
link.
• Phase Lock Loop Verification– verifies the accuracy of the system phase
lock loop upon command from the DEC. The software compares the tim-
ing of the external 5.333 KHZ interrupt with the interrupt generated inter-
nally. If the interrupt timings are not comparable, an error appears.
3-10 Diagnostics