Toshiba T3200 User Manual page 163

C.3 SIGNAL DESCRIPTION AND PIN ASSIGNMENT
TABLE C-l Pin Description
Pin
1/0 Signal Name
Descri ption
CPU hold acknowledge signal.
1
I CPHLDA
When this signal is high, the system bus is used by
any other controller than the CPU.
If this signal is low, the system is used by the CPU.
CPU address latch signal.
2 0
ALE
The address data is latched at falling edge of this
signal.
3
VCC +5V
Address enable signal during the slave DMA
4
I AEN1 operation. The DMA address is enabled when
this signal is low.
1/0 read command.
S 1/0 lOR
1/0 read operation is executed when this signal is
low. In the master mode, this becomes an input
signal.
1/0 write command.
1/0 write operation is executed when this signal is
6 1/0 lOW low. This signal is output from the DMAC
(U8237) during the DMA operation. In the
master mode, this becomes an input signal.
Memory I/O select signal.
7
I MIO
When this Signal is high, memory cycle is being
executed, and when this signal is low, it is 1/0
cycle.
8
0 CLK4
12MHz clock (not used).
Memory read command. This signal is also
output during the memory refresh operation.
9 1/0 MEMR* Memory read operation is done when this signal
is low. In the master mode, this becomes an
input signal.
Memory write command. The write operation is
10
I/O MEMW*
done when this signal is low. In the master
mode, this becomes an input signal.
Clock rate select sig nal.
This signal is generated by the keyboard
11 I SEL4M
controller to select CPU clock rate.
When this signal is low, the CPU clock rate is 12
MHz, and when it is high, the CPU clock rate is 6
MHz.
C-3