Toshiba T3200 User Manual page 149

A.4.3 DMA operation
- Byte DMA operation
DMA data transfer between I/O port connected to the low bank
data bus and memory location of odd address is as follows.
Case of I/O to Memory
Case of Memory to I/O
"D
.. c
(refer to Figure A-2)
- Word DMA operation
The GA is not concerned with the word DMA operation.
~.5 Address Generation
System address busses SA19-SAO are generated in this GA,
and each of these lines are used for the following purposes.
- CPU address output SA19 - SA9
- DMA address output SA19 - SA9, XA8
- Refresh address output : SA8 - SAO
To generate the system address, following three functional
blocks are applied.
A.5.1 SA19 -SA17
SA19 - 17 come from the CPU and from the Memory Mapper GA.
They are wired ORed.
I Alq-A17
>
r
SEL <:lI.1Q"':'<;A17
">
I
>
\=:J
REFADO ;:;
L.CH
ALE
.-
CPHLDA
CPHLD~
+DMACK
FIGURE A-3 System Address Bus 19 - 17
A-9