Toshiba T3200 User Manual page 157

Pin
I/O Signal Name Description
64 I
PDINL
Parity error signal from the system memory (low
bank).
65
GND Ground
Parity error signal from the system memory (high
66
I PDINH
bank). This signal is active low.
It makes an NMI interrupt signal at the rising
edge of the memory read if an error occurs.
Data write command to the real timer.
67
0 RETIMW
This signal becomes active when write operation
to the 1/0 port address 071 H is executed. This
signal is active low.
68 0
STEP
Step signal to the FDD.
This signal is active high.
Seek enable signal to the FDD.
69 I
RWSEK
When this signal is low, FD seek operation is
enabled, and when it is high, FDD read orwrite
operation is enabled.
70 I FDSTEP
Step signal from the FDC.
This signal is active high.
Chip select signal to the DMAC (U8237A).
71 0 DMA1CS This signal becomes active when the 1/0 port
address is OO*H. This signal is active low.
A23--A 17 are used as page address during the
DMA operation. The page address from the
72
0 A23
internal register is output when the DMA
acknowledge signal is low.
Address line bit 23.
73 0 A22 Address line bit 22.
74
0
A21 Address line bit 21.
75 0 A20
Address line bit 20.
76 0 A19
Address line bit 19.
77 0 A18
Address line bit 18.
78 0 Vcc +5V
79 0 A17
Address line bit 17.
80 I $14MHZ
Clock signal (14.31818 MHz) to the timer (U8254).
Each of XA9--XAO is X address which is same as
the system address. They are used to decode the
81 I XAO
1/0 port address or to specify the DMA page
register for readl write operation to the page
address reqister
B-7