Toshiba T3200 User Manual page 155

Pin
1/0 Signal Name
Description
Power on reset signal. This signal is active low.
26 I
PUCLR
This signal inhibits real timer write command
during the reset period.
27
I 10CHK
Error signal from an external expansion unit. If
this signal is low, the NMI flag becomes effective.
28 Vcc
+5V
This signal is to read the interrupt vector address.
29 I INTA
This signal comes from the interrupt controller
(U8259A).
DMA refresh enable signal. This signal is active
30 I REFRSH
high. The Memory Mapper address A23-A 17
and PGA 16 are output during the memory
refresh operation.
31 I TM20UT
Buzzer sound signal used in the system.
This signal comes from the timer (U8254).
32 I RESET
System reset signal.
This signal is active high.
1/0 read command. This signal is active low.
33 I
lOR
It is used to write memory address register in the
GA, system status, and also to generate
command.
1/0 write command. This signal is active low.
34 I
lOW It is used to write memory address sregister in the
GA, or to generate various commands.
35
I
ALE
Address latch enable signal from the
cpu.
This signal is active high.
36
0
TMCLK
Clock signal (1.19 MHz) to the timer (U8254).
Count control signal to the timer.
37 0 TMGATE When this signal is low, it disables from counting,
and when it is high, counting is enabled.
Timer (U8254) chip select signal.
38 0 PITCS This signal is active low, and becomes active
when the 1/0 port address is 04*H-05*H.
Chip select signal to the master interrupt
39
0 PIC1CS
controller (U8259A). This signal is active low, and
becomes active when 1/0 port address is
02*H-03*H.
40 GND Ground
B-5