Toshiba T3200 User Manual page 165

Pin I/O
Signal Name
Description
RealI Protect mode select signal.
30 I REAL
When this signal is low, the CPU is in the real
mode, and when it is high, the CPU is in the
protect mode.
31 0 CLK42
Keyboard controller clock signal (6MHz).
32 0 AS18
Address strobe signal to the real timer
(MC146818). This signal is active low.
33 I $24MHz System clock signal (24 MHz)
CPU ready signal.
34 0
CPRDY
This signal is active low, and is sampled by the
CPU at the leading edge of the Tc cycle.
CPU clock signal.
35 0
CPUCLK
Either 24 MHz or 12 MHz is output by the clock
selection control.
36 I S1 CPU bus status bit 1.
37
I
SO
CPU bus status bit
o.
38
I NDPCS NDP(80287) chip select signal.
39
I TMIOUT Memory refresh request signal
40 GND Ground
41 I TEST Test signal for the GA. This signal is active high.
Peripheral 1/0 select signal. This signal generates
42 I PPICS real timer address strobe signal. When 1/0
address is 06*h/07*h, this signal becomes low.
43 I PUCLR
Power on reset signal. This signal is acitive low.
44 0 DMACLK
DMA clock signal.(4MHz or 2MHz)
Ready signal to the DMAC One wait cycle is
45
0
DMARDY
given in the DMA operation.
When this signal is low, it gives the wait cycle,
and when it is high, DMA operation is is enabled.
Ack hold signal to the external DMAC
46 0
DMHLDA When this signal is high, it allows the DMA
operation.
47 I DMHRQ
CPU hold request signal from the external DMAC
This signal is acitve high.
48 I DMAMRD
Memory read command from the DMAC
This signal is active low.
Slave DMAC cycle signal. This signal is active low.
49 I DACK4
The master DMAC can not output addressl
command signal while this signal is active.
50
I XA4
Address sianal. CPUI DMA address bit 4.
C-5