Toshiba T3200 User Manual page 168

Pin I/O Signal Name
Description
This signal is dummy address for 2nd byte
88
0
CNVAO
transfer in 16/8 bit conversion.
The 1 st byte is latched at raising point of this
signal while read operation is being executed.
This signal specifies the direction of the 2nd byte
transfer in 16/8 bit conversion.
89 0 BCHGDR
When this signal is low;
High bank
~
Low bank
When this signal is high;
Low bank
~
High bank
90 GND Ground
This signal is an enable signal for the 2nd byte
91
O~
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This signal is active low.
92
_0
C:PVHRO
CPU hold request signal. This signal is generated
-- -- --.-------= ---- ---
when the DfVIHRQ signai ishlcih.
~
- - - - - -
-
~-
93
0
CHK2
Internal monitor signal inside the GA.
System memory (0-640 Kbytes) access signal.
94 0 RAM16 This signal is active low. It enables the parity
error detection.
This signal is to latch the dummy address of the
95 0
CNVALE 2nd byte transfer in 16/8 bit conversion. This
siqnal is active high.
Output signal from the EMS GA:
This signal indicates that the memory to be
96 0 LlMSL
accessed is the system memory, and that neither
VRAM nor the memory connected to the
extended bus is accessed.
BIOS ROM chip select signal. This signal is active
97 0
ROMCS
low. The decode ranges of the address are:
OEOOOOH-OFFFFH
FEOOOOH-FFFFFH
System address inverted signal during the CPU
98
0 LATAO
cycle. When this signal is high (SAO is low), low
data bus enable sianal is aenerated.
C-8