Toshiba T3200 User Manual page 195

F.3 SIGNAL DESCRIPTION AND PIN ASSIGNMENT
TABLE G-l Pin Description
Pin
I/O Signal Name Description
1 GND Ground
2
I/O
M3DA-4
Memory data and address bit 4, plane 3.
CPU add ress bit 10 at ESAN.
3 I/O M3DA-5
Memory data and address bit 5, plane 3.
CPU address bit 11 at ESAN.
4 I/O M3DA-6
Memory data and address bit 6, plane 3.
CPU add ress bit 12 at ESAN.
5
I/O M3DA-7
Memory data and address bit 7, plane 3.
CPU address bit 13 at ESAN.
6 I/O M2DA-0
Memory data and address bit 0, plane 2.
CPU address bit 14 at ESAN.
7 I/O M2DA-l
Memory data and address bit 1, plane 2.
LIGHT PEN Switch at ESAN.
8 I/O M2DA-2 Memory data and address bit 2, plane 2.
9
I/O
M2DA-3 Memory data and address bit 3, plane 2.
10
FCVO
Active low, bits DO and Dlof Figure Control
11
0
FCV1
Register at I/O port 3XA; supplied to Feature
Connector.
12 I/O M2DA-4 Memory data and address bit 4, plane 2.
13
I/O M2DA-5 Memory data and address bit 5, plane 2.
14 I/O M2DA-6 Memory data and address bit 6, plane 2.
15 GND Ground
16 I/O M2DA-7 Memory data and address bit 7, plane 2.
17 I/O SDO CPU data bit 1
18 I/O SD1 CPU data bit 2
19
I/O
SD2 CPU data bit 3
20 I/O
SD3
CPU data bit 4
21
Vcc +5V
22
GND
Ground
23 I/O SD4 CPU data bit S
24 I/O SDS CPU data bit 6
25 I/O SD6
CPU data bit 7
26 I/O SD7 CPU data bit 8
Active high, indicates that an interrupt has been
27 I/O
IRQ9
generated. Can be set to high impedance under
program control (3XS-11 H, bitS).
Gets read as STATUS 0 bit 7.
G-4