Toshiba T3200 User Manual page 166

Pin 1/0 Signal Name
Description
51 1/0
XAO
Address signal. This signal is from SAO.
It is input during the slave DMAC operation.
52 0 BUSE N
Data Enable Signal:
This signal is used to enable data bus.
53 Vcc
+5V
PEAK output signal to the NDP:
54 I PAKO
The expanded PAKI (29 pins) signal with one
more CPU clock in order to meet the timing
specifications of the NDP.
Memory read command. This signal is output to
55 0
SMEMR*
the 8-bit expansion bus.
It is not output to any address of more than 1 M
byte. This signal is active low.
56 0
SMEMW *
Memory write command. The output condition
of this signal is same as that of the SMEMR signal.
57 I 10RDY
CPU ready control signal from outside the GA.
When this signal is low, a wait cycle can be qiven.
58
0
DMAAEN
Address enable signal during the DMA
operation. This signal is acive low.
System bus high enable signal.
59 I/O
SBHE
This signal enables the high bank of the data
when it is active. In the master mode, this signal
becomes an input signal.
60 I
1016
This signal defines that 16-bit type of I/O device is
serviced in
110
command execution.
16-bit memory access signal.
61 I MEM16
This signal is to indicate that 16-bit type memory
is accessed.
62 0 SYSCLK
System clock.
One-third of the CPU clock frequency is output.
This signal is output when DMA request signal
63
0 DM1HLD
comes from the slave DMAC. When DACK4 is
low, this signal becomes active (high).
The slave DMAC starts DMA operation by this.
64 I
TEST2
GA test signal: This signal is active high.
65
GND Ground
66
0 AMEMR
Memory read signal to the T3200 system memory
(including expansion memory).
67 I TEST1
GA test sianal: This sianal is active low.
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