Toshiba T3200 User Manual page 143

A.3 SIGNAL DESCRIPTION AND PIN ASSIGNMENT
TABLE A-I Pin Description
Pin
liD
Signal Name
Description
CPU hold acknowledge signal.
1
I CPHLDA When this signal is high, the system bus is used by
anyother controller than the CPU.
2
I ALE
CPU address latch signal.
This signal is active high.
3 Vcc
+ 5V
4
I PGA16
This signal is a part of DMA address from the
page register of the Memory Mapper GA.
Data transfer direction signal in the CPU access
5
I
DIRC
mode. When this signal is low, the data goes to
the CPU (read cycle), and when it is high, the data
comes from the CPU (write cycle).
Data bus enable signal.
6 I BUSEN
This signal controls data enable timing during
the CPU readl write operation.
This signal is active high.
XD7-XDO are data bus from the liD controllers.
7 I XDO
The DMAC outputs DMA address on the data bus
during the DMA operation.
Data bus bit
o.
8 I XD1 Data bus bit 1.
9 I XD2 Data bus bit 2.
10 I
XD3
Data bus bit 3.
11 I XD4 Data bus bit 4.
12 I XD5
Data bus bit 5.
13 I XD6
Data bus bit 6.
14 I XD7
Data bus bit 7.
15
GND Ground
16 I AEN1
Address enable signal for the slave DMA.
This signal is active low.
17 I AEN2
Address enable signal for the master DMA.
This signal is active low.
A 19-A9 are the CPU address lines. These lines
18
I A9
also come from the Memory Mapper GA for the
DMA address transfer.
CPU address line bit 9.
19 I A10 CPU address line bit 10.
20
I A 11 CPU address line bit 11.
21 I A15 CPU address line bit 15.
A-3