Toshiba T3200 User Manual page 154

Pin I/O Signal Name
Description
This signal defines that the NDP (80287) has been
13
0 NDPCS
selected. If this signal is low, the system data bus
is disabled. When OF8H*SMI0*INTA 1 is made,
this signal is activated.
Direction signal for CPU data transfer.
14 I DIRC
When this signal is low, read data is on the data
bus, and when it is high, write data is on the data
bus.
15 GND
Ground
16 I HCS1 HDD address decode signal 1 (not used).
Data (low bank) enable signal.
17
0
DBlEN
This signal is generated from lATAO signal. This
signal is active high.
Data bus (high bank) enable signal.
18 0 DBHEN
This signal is generated from SHBE signal.
This signal is active high. each data bus is
controlled inside the GA.
This signal is read enable signal for the 1st byte
19
0
lATDEN
transfer in 16/8 bit conversion.
The 1st byte has been stored in a buffer of the
Bus Controller GA during the 1st read cycle.
NMI interrupt signal. It is active high.
20
0
NMI
This signal is output when memory parity error or
any error from the expansion unit occurs.
21 0 BSYCPU
CPU busy signal to NDP.
This signal is active low.
I/O channel ready signal:
22
0
10RDY
This signal is used to expand the NDP reset signal
in order to meet the timing specification of the
NDP.
ROM chip select signal. This signal is active low.
23 0 ROMCS
The address ranges are:
OFOOOOH-OFFFFFH
FEOOOOH-FFFFFFH
This signal becomes low when the system
24
I RAM16
memory (0-640 Kbytes) is accessed. This signal
enables internal parity error detection flag.
PeripheralI/O select signal.
25 0 PPICS
This signal becomes active when the I/O port
address is 06*H-07*H.
This signal is active low.
B-4