Toshiba T3200 User Manual page 167

Pin
I/O
Signal Name
Description
Refersh enable signal.
68 I REFRSH
When this signal is high, it enbales internal
memory refresh circuit.
Interrupt vector read signal.
69
0
INTA When this signal is low, system address (SAO)
becomes low.
Memory write signal output from the DMA.
70 0 XMEMW When not in the DMA mode, MEMW signal is
output.
71 I/O SAO System address. (The lowest bit)
72 I/O XIOW
I/O write command from the DMA.
Active low when CPU mode lOW signal is output.
73 I/O XIOR
I/O read command from the DMA.
Active low when CPU mode lOR signal is output.
System address line bit 16.
74 I SA16
SA 16 and SA 15 are used to select the video
memory chips.
75 I SA15 System address line bit 15.
76 0 CHK1 Internal monitor signal in the GA. (not used).
77 I OWAIT It gives 0 wait during the CPU cycle.
78 Vcc +5V
CPU reset signal. This signal is active high.
79 0
CPURST
When switching the power on or off, this signal
becomes active.
80 I
AEN2
Address enable signal during the master DMAC
operation. This signal is active low.
81 I
AMEMW
Memroy write signal to the T3200 system
memory (including
eXJ~anion
memory)
This signal enables or disables to access sytem
82
I RAMOP
memory (512 K-640 Kbytes).
When this is "0", access is enabled, and it is
always set to "0" in this system.
83 0 CRTMCS
Color graphic video memory select signal.
(OB8000H-OBBFFFH)
84 0
RST
System reset. This signal becomes active when
the power is switched on.
85
0 REFIN
Memory refresh enable signal.
This signal is active high.
This signal is from the memory refresh control
86
0
REFQ1
counter. When this signal is low, the refresh
address is output.
87 0 REFADO
Memory refresh address. (The lowest bit)
C-7