Toshiba T3200 User Manual page 144

Pin I/O Signal Name
Descri ption
22 I A12
CPU address line bit 12.
23 I
A13 CPU address line bit 13.
24 I A17
CPU address line bit 17.
25 I
A19 CPU address line bit 19.
26 I A14
CPU address line bit 14.
27 I A16
CPU address line bit 16.
28 Vcc
+5V
29 I
A18 CPU address line bit 18.
This signal is generated by CPHLDA signal.
30 I DMACK When this signal is low, CPU mode is activated,
and when it is high, DMA mode is activated.
31
0
XA8 DMA address
Each of SD15-SDO is the system data bus.
32 I/O SD15
The lines SD15-SD8 are in the high bank, while
SD7-SDO are in the low bank.
System data bus bit 15.
33
I/O SD14
System data bus bit 14.
34 I/O SD13 System data bus bit 13.
35 I/O SD12 System data bus bit 12.
36 I/O SD11
System data bus bit 11.
37 I/O
SD10 System data bus bit 10.
38
I/O
SD9 System data bus bit 9.
39 I/O SD8 System data bus bit 8.
40 GND Ground
41
I/O SD7
System data bus bit 7.
42 I/O SD6 System data bus bit 6.
43 I/O SD5 System data bus bit 5.
44 I/O SD4 System data bus bit 4.
45 I/O SD3
System data bus bit 3.
46 I/O SD2 System data bus bit 2.
47 I/O SD1 System data bus bit 1.
48 I/O SDO System data bus bit
o.
This is an enable signal to transfer the 2nd byte
49 I BCHGEN
during 16/8 bit conversion.
It is also enabled while DMA byte is transferred.
This signal is active low.
This signal controls the direction of the 2nd byte
50 I BCHGDR transfer during 16/8 bit conversion or DMA byte
transfer.
A-4