Toshiba T3200 User Manual page 189

Pin 1/0 Signal Name
Description
28 Vcc
+ 5V
29 I
PORE CRT display signal from the PEGA2.
30 I POSR CRT display signal from the PEGA2.
31
0
READ PEGA read I write select signal
32 0 10SEl I/O select signal
33 0 MEMSl PEGA memory select signal
34
0 ROMSl ROM chip select signal
35 I ClKMUX Basic clock for CRT display
36 I PDPSl Plasmal CRT select signal
This signal is to indicate that the content of the
37
I UNl port 3D8 has already been read twice.
This is cleared by the next read or write signal.
38 0 ClK Basic clock for display. This is output to the PEGA.
39 I ClKPDP Basic clock for Plasma display
40 GND Ground
41 GND Ground
This signal is to enable the SR signal.
42
0
SRON When this is high, CRT output pin No.2 is
grounded.
43
0
SlT NMI generate timing signal
44 0 M3DA2
Address data bit 2 of the DRAM plane 3. In this
GA, system address bus is output to the PEGA.
45 0 M3DA1
Address data bit 1 of the DRAM plane 3.
46 0 M3DAO
Address data bit 0 of the DRAM plane 3.
I/O port address bit 8 for display
47 I XA8
When XA8 = SA8, the port 3XX is accessed.
" XA8 = SA8, the port 2XX is accessed.
PEGA system address input enable signal.
48
I ESA
When this is low, system address is output to M3
bus.
49 0 TRP
Trap (NMI) generate signal
50 0 PEPD4
Plasma display signal. This signal is active low.
Pins 51,54,55,57,58,59,60,61 are used for
selection of CRT or Plasma display as follows,
depending on their combinations.
CRT PDP
PEVS (Pin 58)
9Pin VS
PEGR
PEHS (Pin 59)
8pin HS
51 0
PESB (Pin 54) 7pin
PD1
PESG (pin 55)
6pin
PS4
PEBl (pin 61) Spin
PS3
PEGR (pin 51) 4pin
PS2
PERE (pin 57) 3pin
PS1
PESR (pin 60) 2pin SCK
F-4