Toshiba T3200 User Manual page 164

Pin I/O Signal Name
Description
Output address line from the CPU.
This signal is controlled inside the GA, depending
12
I CPUA20
on the CPU mode {Reali Protect}.
In the real mode, A20 is fixed to low, and in the
protect mode, CPUA2 is output to A20.
CPU reset command.
13 I
RSTCMD
This signal is effective when it is low, and it
outputs the CPU reset signal.
14
I AO
CPU address line bit O.
This signal generates SAO inside the GA.
15
GND
Ground
16 0
DIR
This signal shows the direction of data transfer.
When reading, this becomes low.
17 0
FREQ
Refresh timing signal {not used}.
18 0 BALE
In the CPU mode, this signal functions exactly like
ALE. Apart from the CPU mode, it is always high.
19 0 NPCK Clock signal8MHz forthe NDP {80287}.
CPU address line bit 1 :
20 I A01
This signal is used to generate the "shut down"
signal.
CPUI Memory mapper address.
Memory Mapper address is input during the
21
I A17 DMA operation. This signal is used to decode
each memory size.
CPUI Memory Mapper Address line bit 17.
22 I
A18 Address line bit 18.
23 I
A19 Address line bit 19.
Address line bit 20.
This signal is output during the CPU operation,
24
liD
A20
and when used in the real mode, it is fixed to
low, while in the protect mode, CPUA2 signal is
output. When the CPU is inactivated, this
becomes an input signal.
25 I A21 Address line bit 21.
26 I
A22 Address line bit 22.
27
I A23 Address line bit 23.
28 I
Vcc + 5V
29 I PAKI Input PEACK siqnal from the CPU.
C-4